Low Power Features
2
Low Power Features
2.1
Clock Control and Low Power States
The Celeron M processor supports the AutoHALT Power-Down, Stop Grant, Sleep, Deep
Sleep states for optimal power management. See Figure 1 for a visual representation of
the processor low-power states.
Figure 1.
Clock Control States
SLP# asserted
STPCLK# asserted
Stop
Grant
Normal
Sleep
STPCLK# deasserted
SLP# deasserted
STPCLK#
asserted
halt
break
DPSLP#
de-asserted
DPSLP#
asserted
snoop
serviced
HLT
snoop
occurs
STPCLK#
deasserted
instruction
snoop
occurs
HALT/
Grant
Snoop
Deep
Sleep
Auto Halt
snoop
serviced
V0001-04
Halt break - A20M#, INIT#, INTR, NMI, PREQ#, RESET#, SMI#, or APIC interrupt
2.1.1
2.1.2
Normal State
This is the normal operating state for the processor.
AutoHALT Power-Down State
AutoHALT Power-Down is a low-power state entered when the processor executes the
HALT instruction. The processor will transition to the Normal state upon the occurrence
of SMI#,INIT#, LINT[1:0] (NMI, INTR), or FSB interrupt message. RESET# will cause
the processor to immediately initialize itself.
The system can generate a STPCLK# while the processor is in the AutoHALT Power-
Down state. When the system deasserts the STPCLK# interrupt, the processor will
return execution to the HALT state. While in AutoHALT Power-Down state, the processor
will process bus snoops and interrupts.
2.1.3
Stop-Grant State
When the STPCLK# pin is asserted, the Stop-Grant state of the processor is entered 20
bus clocks after the response phase of the processor issued Stop-Grant Acknowledge
special bus cycle.
Datasheet
11
INTEL [ INTEL ]
