Electrical Specifications
Figure 6.
Deep Sleep VCC and ICC Loadline for Celeron M Processors:
Standard Voltage and Ultra Low Voltage
VCC [V]
Slope= -3.0 mV/A
10mV= RIPPLE
Vcc nom - 1.2%
+/-1.5% from Nominal =VR Error
I CC
[A]
ICC
0
max
Deep Sleep
Table 8.
Symbol
FSB Differential BCLK Specifications
Parameter
Min
Typ
Max
Unit
Notes1
VIH
Input High Voltage
Input Low Voltage
Crossing Voltage
0.660
0.710
0
0.850
V
V
VIL
VCROSS
ΔVCROSS
VTH
0.25
N/A
0.35
N/A
0.55
0.140
V
2
6
3
4
5
Range of Crossing Points
Threshold Region
V
VCROSS - 0.100
VCROSS + 0.100
± 100
V
ILI
Input Leakage Current
Pad Capacitance
µA
pF
Cpad
1.8
2.3
2.75
NOTES:
1.
2.
Unless otherwise noted, all specifications in this table apply to all processor frequencies.
Crossing Voltage is defined as absolute voltage where rising edge of BCLK0 is equal to the falling edge of
BCLK1.
3.
Threshold Region is defined as a region entered about the crossing voltage in which the differential receiver
switches. It includes input threshold hysteresis.
4.
5.
6.
For Vin between 0 V and VIH.
Cpad includes die capacitance only. No package parasitics are included.
ΔVCROSS is defined as the total variation of all crossing voltages as defined in note 2.
26
Datasheet
INTEL [ INTEL ]
