Processor Configuration Registers
2.19.8
RP_STATE_CAP—RP State Capability Register
This register contains the maximum base frequency capability for the Integrated
Graphics Engine (GT).
B/D/F/Type:
Address Offset:
Reset Value:
Access:
0/0/0/MCHBAR PCU
5998–599Bh
00000000h
RO-FW
32 bits
00h
Size:
BIOS Optimal Default
Reset
Value
RST/
PWR
Bit
Access
Description
31:24
RO
0h
Reserved (RSVD)
RPN Capability (RPN_CAP)
This field indicates the maximum RPN base frequency capability
for the Integrated Graphics Engine (GT). Values are in units of
100 MHz.
23:16
15:8
7:0
RO-FW
RO-FW
RO-FW
00h
Uncore
Uncore
Uncore
RP1 Capability (RP1_CAP):
This field indicates the maximum RP1 base frequency capability
for the Integrated Graphics Engine (GT). Values are in units of
100 MHz.
00h
00h
RP0 Capability (RP0_CAP):
This field indicates the maximum RP0 base frequency capability
for the Integrated Graphics Engine (GT). Values are in units of
100 MHz.
2.19.9
PCU_MMIO_FREQ_CLIPPING_CAUSE_STATUS Register
This register provides the status of the frequency clipping cause in MMIO for both
Power plane 0 (IA) and Power plane 1 (GT)
B/D/F/Type:
Address Offset:
Reset Value:
Access:
0/0/0/MCHBAR PCU
5C20–5C23h
00000000h
RW
Size:
32 bits
Reset
Value
RST/
PWR
Bit
Access
Description
pp1_clipped
Set if the PP1 (GT) frequency requested was clipped.
31
30
RW
RW
00000000h
00000000h
Uncore
Reserved (RSVD)
pp1_clipped_non_turbo
29
28:25
24
RW
RW
RW
RW
RW
00000000h
00000000h
00000000h
00000000h
00000000h
Uncore
Set if the PP1 (GT) frequency requested was clipped, but current
frequency is lower than RP1 (MAX_NON_TURBO).
Reserved (RSVD)
pp1_clipped_edp
Set if the PP1 (GT) frequency requested was clipped by EDP limit
(Vmax, Iccmax, Reliability, and so on).
Uncore
23
Reserved (RSVD)
pp1_clipped_hot_vr
Set if the PP1 (GT) frequency requested was clipped by HOT
indication from VR on SVID.
22
Uncore
Uncore
p1_clipped_pl2
Set if the PP1 (GT) frequency requested was clipped by PL2
(POWER_LIMIT_2) power limiting algorithm.
21
RW
00000000h
302
Datasheet, Volume 2