Processor Configuration Registers
2.19.6
GT_PERF_STATUS—GT Performance Status Register
This register provides the P-state encoding for the Secondary Power Plane’s current PLL
frequency and the current VID.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
0/0/0/MCHBAR PCU
5948–594Bh
00000000h
RO-V
32 bits
0000h
Size:
BIOS Optimal Default
Reset
Value
RST/
PWR
Bit
31:16
15:8
7:0
Access
RO
Description
0h
Reserved (RSVD)
RP-State Ratio (RP_STATE_RATIO)
This field provides the ratio of the current RP-state.
RO-V
RO-V
00h
00h
Uncore
Reserved (RSVD)
2.19.7
RP_STATE_LIMITS—RP-State Limitations Register
This register allows software to limit the maximum base frequency for the Integrated
Graphics Engine (GT) allowed during run-time.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
0/0/0/MCHBAR PCU
5994–5997h
000000FFh
RW
32 bits
000000h
Size:
BIOS Optimal Default
Reset
Value
RST/
PWR
Bit
Access
Description
31:8
RO
0h
Reserved (RSVD)
RP-State Limit (RPSTT_LIM)
7:0
RW
FFh
Uncore
This field indicates the maximum base frequency limit for the
Integrated Graphics Engine (GT) allowed during run-time.
Datasheet, Volume 2
301
INTEL [ INTEL ]
