Processor Configuration Registers
2.3
System Address Map
The processor supports 512 GB (39 bit) of addressable memory space and 64 KB+3 of
addressable I/O space.
This section focuses on how the memory space is partitioned and the use of the
separate memory regions. I/O address space has simpler mapping and is explained
near the end of this section.
The processor supports PEG port upper prefetchable base/limit registers. This allows
the PEG unit to claim I/O accesses above 32 bit. Addressing of greater than 4 GB is
allowed on either the DMI Interface or PCI Express* (PCIe*) interface. The processor
supports a maximum of 32 GB of DRAM. No DRAM memory will be accessible above 32
GB. DRAM capacity is limited by the number of address pins available. There is no
hardware lock to stop someone from inserting more memory than is addressable.
When running in internal graphics mode, processor initiated TileX/Tiley/linear
reads/writes to GMADR range are supported. Write accesses to GMADR linear regions
are supported from both DMI and PEG. GMADR write accesses to tileX and tileY regions
(defined using fence registers) are not supported from DMI or the PEG port. GMADR
read accesses are not supported from either DMI or PEG.
In the following sections, it is assumed that all of the compatibility memory ranges
reside on the DMI Interface. The exception to this rule is VGA ranges, which may be
mapped to PCI Express, DMI, or to the internal graphics device (IGD). In the absence
of more specific references, cycle descriptions referencing PCI should be interpreted as
the DMI Interface/PCI, while cycle descriptions referencing PCI Express or IGD are
related to the PCI Express bus or the internal graphics device respectively. The
processor does not remap APIC or any other memory spaces above TOLUD (Top of Low
Usable DRAM). The TOLUD register is set to the appropriate value by BIOS. The
remapbase/remaplimit registers remap logical accesses bound for addresses above
4 GB onto physical addresses that fall within DRAM.
The Address Map includes a number of programmable ranges:
• Device 0:
— PXPEPBAR – PxP egress port registers. (4 KB window)
— MCHBAR – Memory mapped range for internal MCH registers. (32 KB window)
— DMIBAR –This window is used to access registers associated with the
processor/PCH Serial Interconnect (DMI) register memory range. (4 KB
window)
— GGC.GMS – Graphics Mode Select. Used to select the amount of main memory
that is pre-allocated to support the internal graphics device in VGA (non-linear)
and Native (linear) modes. (0–1 GB options).
— GGC.GGMS – GTT Graphics Memory Size. Used to select the amount of main
memory that is pre-allocated to support the Internal Graphics Translation Table.
(0–2 MB options).
For each of the following five device functions:
• Device 1, Function 0: (PCIe* x16 Controller)
• Device 1, Function 1: (PCIe x8 Controller)
• Device 1, Function 2: (PCIe x4 Controller)
Datasheet, Volume 2
17
INTEL [ INTEL ]
