Processor Configuration Registers
2.10.9
PBUSN—Primary Bus Number Register
This register identifies that this "virtual" Host-PCI Express* bridge is connected to PCI
bus 0.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
0/6/0/PCI
18h
00h
RO
8 bits
Size:
Reset
Value
RST/
PWR
Bit
Access
Description
Primary Bus Number (BUSN)
Configuration software typically programs this field with the
number of the bus on the primary side of the bridge. Since the
processor root port is an internal device and its primary bus is
always 0, these bits are read only and are hardwired to 0.
7:0
RO
00h
Uncore
2.10.10 SBUSN—Secondary Bus Number Register
This register identifies the bus number assigned to the second bus side of the "virtual"
bridge; that is, to PCI Express-G. This number is programmed by the PCI configuration
software to allow mapping of configuration cycles to PCI Express-G.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
0/6/0/PCI
19h
00h
RW
8 bits
Size:
Reset
Value
RST/
PWR
Bit
Access
Description
Secondary Bus Number (BUSN)
7:0
RW
00h
Uncore
This field is programmed by configuration software with the bus
number assigned to PCI Express-G.
2.10.11 SUBUSN—Subordinate Bus Number Register
This register identifies the subordinate bus (if any) that resides at the level below PCI
Express-G. This number is programmed by the PCI configuration software to allow
mapping of configuration cycles to PCI Express-G.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
0/6/0/PCI
1Ah
00h
RW
8 bits
Size:
Reset
Value
RST/
PWR
Bit
Access
Description
Subordinate Bus Number (BUSN)
This register is programmed by configuration software with the
number of the highest subordinate bus that lies behind the
processor root port bridge. When only a single PCI device resides
on the PCI Express-G segment, this register will contain the same
value as the SBUSN1 register.
7:0
RW
00h
Uncore
Datasheet, Volume 2
169
INTEL [ INTEL ]
