Introduction
1 Introduction
The Intel® Xeon® Processor E7-8800/4800/2800 Product Families are a next-
generation Intel® Xeon® multi-core MP family processor. The processor uses Intel®
QuickPath Interconnect (Intel® QPI) technology, implementing up to four high-speed
serial point-to-point links. It is optimized for MP configurations targeted at enterprise
and technical computing applications, delivering server-class RAS and performance.
Intel Xeon Processor E7-8800/4800/2800 Product Families are multi-core processors,
based on 32-nm process technology. The processors feature Intel QuickPath
Interconnect point-to-point links capable of up to 6.4 GT/s, up to 30 MB of shared
cache, and an integrated memory controller. The processors support all the existing
Streaming SIMD Extensions 2 (SSE2), Streaming SIMD Extensions 3 (SSE3) and
Streaming SIMD Extensions 4 (SSE4). The processors support several Advanced
Technologies: Execute Disable Bit, Intel® 64 technology, Enhanced Intel SpeedStep®
technology, Intel® Virtualization technology (Intel® VT), and Simultaneous Multi-
Threading.
®
®
Feature
Cache Sizes
Intel Xeon Processor E7-8800/4800/2800 Product Families
Instruction Cache (L1) = 32 KB/core (I) and16 KB/core (D)
Data Cache (L2) = 256 KB/core
Last Level Cache (L3) = 30 MB shared among cores
Data Transfer Rate
Multi-Core Support
Up to four full-width Intel QuickPath Interconnect links, up to 6.4 GT/s in
each direction
Up to 10 cores per processor
Multiple Processor Support Dependent on SKU, and supporting silicon. Minimum of two CPUs.
Package
1567-land FCLGA
1.1
Terminology
A ‘_N’ after a signal name refers to an active low signal, indicating that a signal is in the
asserted state when driven to a low level. For example, when RESET_N is low (that is,
when RESET_N is asserted), a reset has been requested. Conversely, when TCK is high
(that is, when TCK is asserted), a test clock request has occurred.
• Enhanced Intel SpeedStep technology — Enhanced Intel SpeedStep technology
allows the O/S to reduce power consumption when performance is not needed.
• Eye Definitions — The eye at any point along the data channel is defined to be the
creation of overlapping of a large number of UI of the data signal and timing width
measured with regards to the edges of a separate clock signal at any other point.
Each differential signal pair by combining the D+ and D- signals produces a signal
eye. A _DN and _DP after a signal name refers to a differential pair.
• FCLGA-1567 — The Intel Xeon Processor E7-8800/4800/2800 Product Families
are available in a Flip-Chip Land Grid Array (FC-LGA) package, consisting of 10
processor cores mounted on a pinned substrate with an integrated heat spreader
(IHS).
• Functional Operation — Refers to the normal operating conditions in which all
processor specifications, including DC, AC, system bus, signal quality, mechanical,
and thermal, are satisfied.
Datasheet Volume 1 of 2
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INTEL [ INTEL ]
