Figures
2-1
VCC Static and Transient Tolerance ..................................................................... 24
Vcache Static and Transient Tolerance ................................................................. 25
Overshoot Example Waveform ............................................................................ 26
Active ODT for a Differential Link Example............................................................ 26
Validation Topology for Testing Specifications of the Reference Clock ....................... 27
Differential Waveform Measurement Points........................................................... 27
Setup for Validating Standalone Tx Voltage and Timing Parameters.......................... 28
Setup for Validating Tx + Worst-Case Interconnect Specifications ............................ 29
Required Receiver Input Eye (Differential) Showing Minimum Voltage Specs ............. 39
2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-9
2-10 Input Device Hysteresis ..................................................................................... 42
2-11 RESET_N SEtup/Hold Time for Deterministic RESET_N Deassertion .......................... 45
2-12 THERMTRIP_N Power Down Sequence.................................................................. 45
2-13 VID Step Times................................................................................................. 46
2-14 SMBus Timing Waveform.................................................................................... 47
2-15 SMBus Valid Delay Timing Waveform ................................................................... 47
2-16 FLASHROM Timing Waveform.............................................................................. 48
2-17 TAP Valid Delay Timing Waveform ....................................................................... 48
2-18 Test Reset (TRST_N), Force_PR_N, RESET_N and PROCHOT_N Pulse Width
Waveform ........................................................................................................ 49
2-19 Intel QPI System Interface Electrical Test Setup for Validating
Standalone TX Voltage and Timing Parameters...................................................... 49
2-20 Intel QPI System Interface Electrical Test Setup for Validating
TX + Worst-Case Interconnect Specifications ........................................................ 50
2-21 Differential Clock Waveform................................................................................ 50
2-22 Differential Clock Crosspoint Specification............................................................. 51
2-23 System Common Clock Valid Delay Timing Waveform ............................................ 51
2-24 Differential Measurement Point for Ringback ......................................................... 51
2-25 Differential Measurement Points for Rise and Fall time............................................ 52
2-26 Single-Ended Measurement Points for Absolute Cross Point and Swing...................... 52
2-27 Single-Ended Measurement Points for Delta Cross Point.......................................... 52
2-28 Voltage Sequence Timing Requirements ............................................................... 53
2-29 VID Step Times and Vcc Waveforms .................................................................... 54
3-1
3-2
3-3
3-4
3-5
6-1
6-2
6-3
6-4
6-5
6-6
6-7
6-8
6-9
Processor Package Assembly Sketch .................................................................... 57
Processor Package Drawing (Sheet 1 of 2)............................................................ 59
Processor Package Drawing (Sheet 2 of 2)............................................................ 60
Processor Top-Side Markings .............................................................................. 62
Processor Land Coordinates and Quadrants, Top View ............................................ 63
130W TDP Processor Thermal Profile.................................................................. 113
105W TDP Processor Thermal Profile.................................................................. 114
95W TDP Processor Thermal Profile.................................................................... 116
Case Temperature (TCASE) Measurement Location .............................................. 117
Intel® Thermal Monitor 2 Frequency and Voltage Ordering ................................... 119
Ping()............................................................................................................ 123
Ping() Example ............................................................................................... 123
GetDIB()........................................................................................................ 124
Device Info Field Definition............................................................................... 124
6-10 Revision Number Definition............................................................................... 125
6-11 GetTemp() ..................................................................................................... 125
6-12 GetTemp() Example......................................................................................... 126
6-13 PCI Configuration Address ................................................................................ 126
6-14 PCIConfigRd()................................................................................................. 127
Datasheet Volume 1 of 2
5
INTEL [ INTEL ]
