Features
7.3.3
PIROM and Scratch EEPROM Supported SMBus
Transactions
The PIROM responds to two SMBus packet types: Read Byte and Write Byte. However,
since the PIROM is write-protected, it will acknowledge a Write Byte command but
ignore the data. The Scratch EEPROM responds to Read Byte and Write Byte
commands. Table 7-2 illustrates the Read Byte command. Table 7-3 illustrates the
Write Byte command.
In the tables, ‘S’ represents a SMBus start bit, ‘P’ represents a stop bit, ‘A’ represents
an acknowledge (ACK), and ‘///’ represents a negative acknowledge (NACK). The
shaded bits are transmitted by the PIROM or Scratch EEPROM, and the bits that aren’t
shaded are transmitted by the SMBus host controller. In the tables, the data addresses
indicate 8 bits.
The SMBus host controller should transmit 8 bits with the most significant bit indicating
which section of the EEPROM is to be addressed: the PIROM (MSB = 0) or the Scratch
EEPROM (MSB = 1).
Table 7-2.
Read Byte SMBus Packet
Slave
Address
Command
Code
Slave
Address
S
Write
A
A
S
Read
A
Data
///
P
1
7-bits
1
1
8-bits
1
1
7-bits
1
1
8-bits
1
1
Table 7-3.
Write Byte SMBus Packet
Slave
Address
Command
Code
S
Write
A
A
Data
A
P
1
7-bits
1
1
8-bits
1
8-bits
1
1
7.4
SMBus Memory Component Addressing
Of the addresses broadcast across the SMBus, the memory component claims those of
the form “10100XXZb”. The “XX” bits are defined by pull-up and pull-down of the
SKTID[1:0] pins. Note that SKTID[2] does not affect the SMBus address for the
memory component. These address pins are pulled down weakly (10 k) on the
processor substrate to ensure that the memory components are in a known state in
systems which do not support the SMBus (or only support a partial implementation).
The “Z” bit is the read/write bit for the serial bus transaction.
Note that addresses of the form “0000XXXXb” are Reserved and should not be
generated by an SMBus master.
Table 7-4 describes the address pin connections and how they affect the addressing of
the memory component.
Datasheet Volume 1 of 2
149
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