Features
7 Features
7.1
Introduction
The Intel Xeon Processor E7-8800/4800/2800 Product Families processor package
includes PECI 2.0, TAP and SMBus interfaces which allow access to processor’s package
information. The processor die is connected to the PECI2.0 and TAP, and these
interfaces can be used for access to the configuration registers of the processor. The
processor Information ROM (PIROM) and scratch EEROM, are accessed via the SMBus
connection.
Figure 7-1. Logical Schematic of Intel® Xeon® Processor E7-8800/4800/2800 Product
Families Package
Package Pins
Level Shifter
GTL2003
Level Shifter
GND
GND
EEPROM
34C02
PCA9509
Processor
Die
Note:
Actual implementation may vary. This figure is provided to offer a general understanding of the architecture.
Datasheet Volume 1 of 2
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