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325119-001 参数 Datasheet PDF下载

325119-001图片预览
型号: 325119-001
PDF下载: 下载PDF文件 查看货源
内容描述: 英特尔® Xeon®处理器E7-8800 / 2800分之4800产品系列 [Intel® Xeon® Processor E7-8800/4800/2800 Product Families]
分类和应用:
文件页数/大小: 174 页 / 3951 K
品牌: INTEL [ INTEL ]
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Features  
Offset/  
Section  
# of  
Bits  
Function  
Notes  
Examples  
Part Numbers  
54-5Ah  
5B-62h  
63-64h  
65h  
56  
Processor Family Number  
Processor SKU Number  
Reserved  
Seven 8-bit ASCII characters  
Seven 8-bit ASCII characters  
Reserved for future use  
1 byte checksum  
AT80604  
003771AA  
0000h  
64  
16  
8
Checksum  
Add up by byte and take 2’s  
complement.  
Thermal Reference  
1
66h  
8
Recommended THERMALERT_N  
assertion threshold value  
MSB is Reserved  
MSB is Reserved  
0h = 0C  
1
67h  
68h  
8
8
Thermal calibration offset value  
0h = 0C  
1
T
Maximum  
Maximum case temperature  
Two 4-bit hex digits (mV)  
69h = 69°C  
CASE  
1
69-6Ah  
6Bh  
16  
8
Thermal Design Power  
Checksum  
Four 4-bit hex digits (in Watts)  
1 byte checksum  
0130h = 130 Watts  
Add up by byte and take 2’s  
complement.  
Features  
6C-6Fh  
32  
8
Processor Core Feature Flags  
Processor Feature Flags  
From CPUID function 1, EDX  
contents  
4387FBFFh  
10001101  
70h  
Eight features - Binary  
1 indicates functional feature  
71h  
72  
8
Additional Processor Feature  
Flags  
Eight additional features - Binary  
1 indicates functional feature  
01110101  
6/2  
4/4  
Multiprocessor Support  
00b = UP, 01b = DP, 10b = S2S,  
11b = MP/SMS  
00000011 = MP/SMS  
1
73h  
Number of Devices in TAP Chain  
First four bits reserved  
One 4-bit hex digit - Bits  
*0h  
74-75h  
76h  
16  
8
Reserved  
Reserved for future use  
1 byte checksum  
0000h  
Checksum  
Add up by byte and take 2’s  
complement.  
Other  
77-7Eh  
64  
8
Processor Serial/Electronic  
Signature  
Coded binary  
N/A  
7Fh  
Checksum  
1 byte checksum  
Add up by byte and take 2’s  
complement.  
Notes:  
1. Uses Binary Coded Decimal (BCD) translation.  
7.3.2  
Scratch EEPROM  
Also available in the memory component on the processor SMBus is an EEPROM which  
may be used for other data at the system or processor vendor’s discretion. The data in  
this EEPROM, once programmed, can be write-protected by asserting the active-high  
SM_WP signal. This signal has a weak pull-down (10 kΩ) to allow the EEPROM to be  
programmed in systems with no implementation of this signal. The Scratch EEPROM  
resides in the upper half of the memory component (addresses 80 - FFh). The lower  
half comprises the Processor Information ROM (addresses 00 - 7Fh), which is  
permanently write-protected by Intel.  
148  
Datasheet Volume 1 of 2  
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