Signal Definitions
Table 5-1.
Signal Definitions (Sheet 4 of 6)
Name
Type
Description
PWRGOOD
I
The processor requires this signal to be a clean indication that all Intel Xeon
Processor E7-8800/4800/2800 Product Families processor clocks and power supplies
are stable and within their specifications. “Clean” implies that the signal will remain
low (capable of sinking leakage current), without glitches, from the time that the
power supplies are turned on until they come within specification. The signal must
then transition monotonically to a high state. PWRGOODcan be driven inactive at any
time, but clocks and power must again be stable before a subsequent rising edge of
PWRGOOD.
The PWRGOOD signal must be supplied to the processor at 1.1V. This signal is used
to protect internal circuits against voltage sequencing issues. It should be driven
high throughout boundary scan operation. VCCSTBY33 signal should be stable for 10
SYSCLOCKs before PWRGOOD is asserted.
QPI[3:0]_DRx_D[P/N][19:0],
QPI[3:0]_CLKRX_D[P/N]
I
O
I
These Intel QPI input data signals provide means of communication between two
Intel QPI ports via one uni-directional transfer link (In). The Rx links, are terminally
ground referenced. These signals can be configured as a full width link with 20 active
lanes, a half width link with 10 active lanes or as a quarter width link with five active
lanes.
Intel QPI
Interface
3:0
R
P/N
DAT[19:0]
Interface
Name
Port Number Receiver
Differential
Pair
Lane
Number
Polarity
Positive/
Negative
Example: QPI4RPDAT[0] represents Intel QPI port 5 Data, lane 0,receive signal and
Positive bit of the differential pair.
QPI[3:0]_DTX_D[P/
N][19:0],QPI[3:0]_clkTX_D[P/N]
These Intel QPI output data signals provide means of communication between two
Intel QPI ports via one uni-directional transfer link (Out).The links, Tx, are terminally
ground referenced. These signals can be configured as a full width link with 20 active
lanes, a half width link with 10 active lanes or as a quarter width link with five active
lanes.
Intel QPI
Interface
3:0
T
P/N
DAT[19:0]
Interface
Name
Port Number Transmitter
Differential
Pair
Lane
Number
Polarity
Positive/
Negative
Example: QPI4RPDAT[0] represents Intel QPI port 5 Data, lane 0,Transmit signal and
Positive bit of the differential pair.
RESET_N
Asserting the RESET_N signal resets the processor to a known state and invalidates
its internal caches without writing back any of their contents. BOOTMODE[0:1]
signals are sampled at the active-to-inactive transition of RESET_N for selecting
appropriate BOOTMODE. Also RUNBIST is sampled at the active-to-inactive
transition of RESET_N to select BIST operation.
RSVD
These Pins are reserved and should be treated as NO CONNECT, left unconnected.
RUNBIST
I
I
I
This input pin is sampled on a active-to-inactive transition of RESET_N. If sampled
high, this enables BIST (Recommended).
SKTDIS_N
Sampled with the rising edge of RESET_N input. Asserted, signal will disable the
socket, tri-state I/O.
SKTID[2:0]
Socket ID strapping pins. These pins determine the addresses to be used on the
SMBus to access the processor.
SKTOCC_N
SM_WP
O
I
Static signal, asserted low when the socket is occupied with processor.
WP (Write Protect) can be used to write protect the Scratch EEPROM. The Scratch
EEPROM is write-protected when this input is pulled high to VCCSTBY33.
108
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