Signal Definitions
Table 5-1.
Signal Definitions (Sheet 3 of 6)
Name
FBD1SBOCLK[C/D][P/N]0
Type
Description
O
These differential pair output clock signals generated from Intel Xeon Processor E7-
8800/4800/2800 Product Families processor are inputs to the branch one, channel C
and D of Intel® SMI links.
Intel
SMI
1
SB
O
CLK
C/D
P/N
Interface
Name
Branch
South
Output
Clock
Channel Differential
Pair
Number Bound
Polarity
Positive/
Negative
Example: FBD1SBICLKAP0 Intel SMI branch 1, south bound clock output signal of
channel A and positive bit of the differential pair.
FLASHROM_CFG[2:0]
I
These are input signals to the Intel Xeon Processor E7-8800/4800/2800 Product
Families processor that would initialize and map the serial Flash ROM upon reset.
After the reset is deasserted this input would be ignored by the processor logic.
FLASHROM_CLK
FLASHROM_CS[3:0]_N
FLASHROM_DATI
FLASHROM_DATO
FLASHROM_WP_N
FORCE_PR_N
O
O
I
Serial flash ROM clock.
Serial Flash ROM chip selects. Up to four separate flash ROM parts may be used.
Serial Data Input (from ROM(s) to processor).
Serial Data Output (from processor to ROM(s)).
Flash ROM write-protect.
O
O
I
Force processor power reduction by activation of a TCC.
Current sense for Vcore VR11.1
ISENSE_D[N/P]
LT-SX (Test-Lo)
IO
I
In platforms supporting the Intel TXT feature, the Intel TXT pin on the processor
should be variable setting and driven based on the processor type installed. With
Intel Xeon Processor E7-8800/4800/2800 Product Families processor installed, the
Intel TXT pin should be driven high to support Intel TXT. With Intel® Xeon®
processor 7500 series installed the Intel TXT pin should be driven low. Note that TXT
is not supported on the Intel® Xeon® processor 7500 series. On platforms not
supporting the TXT feature, the pin can be strapped low. For Intel® Xeon®
processor 7500 series debug purposes, you will need that ability to pull Intel TXT
low.
MBP[7:0]
IO
I
Sideband signals connecting to XDP header for Run-time control and debug.
MEM_THROTTLE[1:0]_N
When asserted, the internal memory controllers throttle the memory command issue
rate to a configurable fraction of the nominal command rate settings.
MEM_Throttle[1] corresponds to mem_ctrl behind the HA xxx 11, and
MEM_Throttle[0] corresponds to mem_ctrl behind HA xxx 01.
NMI
I
IO
O
I
Interrupt input. Active high. Must be minimum of three clocks.
Processor Sideband Access via PECI interface.
Processor debug interface.
PECI
PRDY_N
PREQ_N
Proc_ID[1:0]
Processor debug interface.
O
Processor ID. 11: Intel® Xeon® processor 7500. 10: Intel Xeon Processor E7-8800/
4800/2800 Product Families. 01, 00: Reserved for future generations.
PROCHOT_N
O
O
The assertion of PROCHOT_N (processor hot) indicates that the processor die
temperature has reached its thermal limit. Open Drain Output.
PSI_CACHE_N
Vcache Power Status Indicator signal to the VR that the processor is in package C3
or C6 power states so the VR can use fewer phases. This signal has on die
termination of 50 ohms.
PSI_N
O
Vcore Power Status Indicator signal to the VR that the processor is in package C3 or
C6 power states so the VR can use fewer phases. This signal has on die termination
of 50 ohms.
Datasheet Volume 1 of 2
107
INTEL [ INTEL ]
