Signal Definitions
5 Signal Definitions
Table 5-1.
Signal Definitions (Sheet 1 of 6)
Name
Type
Description
BOOTMODE[1:0]
I
The BOOTMODE[1:0] inputs are to specify which mode the Intel Xeon Processor E7-
8800/4800/2800 Product Families processor will boot to. For details on the modes
refer to the Intel® Xeon® Processor 7500 Series Datasheet, Volume 2.
CVID[7:1]
O
IO
IO
I
Voltage ID driven out to the VR 11.1 for dynamic/static adjustment of processor
voltage set point. See VCACHE below. This signal has on die termination.
ERROR[0]_N
Pulsed Signal. As output, signals un-corrected error condition of the processor. As an
input, can be programmed to signal SMI to the cores. Open drain
ERROR[1]_N
Level Signal. As output, signals fatal error condition of the processor. As an input,
can be programmed to signal SMI to the cores. Open drain.
FBD0NBI[A/B][P/N][13:0]
These differential pair data signals generated from the branch zero, channel A and B
of Intel® SMI links are input to the Intel Xeon Processor E7-8800/4800/2800
Product Families processor.
Intel
SMI
0
NB
I
A/B
P/N
[13:0]
Interface
Name
Branch
North
Input
Channel Differential Lane
Number Bound
Pair
Number
Polarity
Positive/
Negative
Example: FBD0NBIAP[0] Intel SMI branch 0, North bound data input lane 0 signal of
channel A and positive bit of the differential pair.
FBD0NBICLK[A/B][P/N]0
I
These differential pair clock signals generated from the branch zero, channel A and B
of Intel® SMI links are input to the Intel Xeon Processor E7-8800/4800/2800
Product Families processor.
Intel
SMI
0
NB
I
CLK
A/B
P/N
Interface Branch
North
Input
Clock
Channel Differential
Pair
Name
Number Bound
Polarity
Positive/
Negative
Example: FBD0NBICLKAP0 Intel SMI branch 0, Northbound clock input signal of
channel A and positive bit of the differential pair.
FBD0SBO[A/B][P/N][10:0]
O
These differential pair output data signals generated from Intel Xeon Processor E7-
8800/4800/2800 Product Families processor to the branch zero, channel A and B of
Intel® SMI links.
Intel
SMI
0
SB
O
A/B
P/N
[10:0]
Interface Branch
Name
South
Output
Channel
Differential Lane
Number Bound
Pair
Number
Polarity
Positive/
Negative
Example: FBD0SBOAP[0] Intel SMI branch 1, southbound data output lane 0 signal
of channel A and positive bit of the differential pair.
Datasheet Volume 1 of 2
105
INTEL [ INTEL ]
