Signal Description
Table 2-6.
PCI Interface Signals (Sheet 3 of 3)
Name
Type
Description
REQ0#
PCI Requests: The ICH10 supports up to 4 masters on the PCI
bus.
REQ1#/ GPIO50
REQ2#/ GPIO52
REQ3#/GPIO54
I
REQ[3:1]# pins can instead be used as GPIO.
PCI Grants: The ICH10 supports up to 4 masters on the PCI bus.
GNT[3:1]# pins can instead be used as GPIO.
GNT0#
Pull-up resistors are not required on these signals. If pull-ups are
used, they should be tied to the Vcc3_3 power rail.
GNT1#/ GPIO51
GNT2#/ GPIO53
GNT3#/GPIO55
O
NOTE: GNT[3:0]# are sampled as a functional strap. See
Section 2.25.1 for details.
PCI Clock: This is a 33 MHz clock. PCICLK provides timing for all
transactions on the PCI Bus.
PCICLK
I
PCI Reset: This is the Secondary PCI Bus reset signal. It is a
logical OR of the primary interface PLTRST# signal and the state of
the Secondary Bus Reset bit of the Bridge Control register
(D30:F0:3Eh, bit 6).
PCIRST#
O
PCI Lock: This signal indicates an exclusive bus operation and may
require multiple transactions to complete. ICH10 asserts PLOCK#
when it performs non-exclusive transactions on the PCI bus.
PLOCK# is ignored when PCI masters are granted the bus.
PLOCK#
SERR#
I/O
System Error: SERR# can be pulsed active by any PCI device that
I/OD detects a system error condition. Upon sampling SERR# active, the
ICH10 has the ability to generate an NMI, SMI#, or interrupt.
PCI Power Management Event: PCI peripherals drive PME# to
wake the system from low-power states S1–S5. PME# assertion can
also be enabled to generate an SCI from the S0 state. In some
cases the ICH10 may drive PME# active due to an internal wake
PME#
I/OD
event. The ICH10 will not drive PME# high, but it will be pulled up
to VccSus3_3 by an internal pull-up resistor.
2.7
Serial ATA Interface
bh
Table 2-7.
Serial ATA Interface Signals (Sheet 1 of 3)
Name
Type
Description
Serial ATA 0 Differential Transmit Pairs: These are outbound
SATA0TXP
SATA0TXN
high-speed differential signals to Port 0.
O
In compatible mode, SATA Port 0 is the primary master of SATA
Controller 1.
Serial ATA 0 Differential Receive Pair: These are inbound high-
SATA0RXP
SATA0RXN
speed differential signals from Port 0.
I
In compatible mode, SATA Port 0 is the primary master of SATA
Controller 1.
Serial ATA 1 Differential Transmit Pair: These are outbound
SATA1TXP
SATA1TXN
high-speed differential signals to Port 1.
O
In compatible mode, SATA Port 1 is the secondary master of SATA
Controller 1.
52
Datasheet
INTEL [ INTEL ]
