Signal Description
2.8
LPC Interface
Table 2-8.
LPC Interface Signals
Typ
Name
e
Description
LAD[3:0] /
FWH[3:0]
LPC Multiplexed Command, Address, Data: For LAD[3:0], internal pull-
ups are provided.
I/O
O
LFRAME# /
LPC Frame: LFRAME# indicates the start of an LPC cycle, or an abort.
FWH4
LPC Serial DMA/Master Request Inputs: LDRQ[1:0]# are used to
request DMA or bus master access. These signals are typically connected
to an external Super I/O device. An internal pull-up resistor is provided on
these signals.
LDRQ0#,
I
LDRQ1# /
GPIO23
LDRQ1# may optionally be used as GPIO.
2.9
Interrupt Interface
Table 2-9.
Interrupt Signals
Name
Type
Description
Serial Interrupt Request: This pin implements the serial interrupt
protocol.
SERIRQ
I/OD
PCI Interrupt Requests: In non-APIC mode the PIRQx# signals can
be routed to interrupts 3, 4, 5, 6, 7, 9, 10, 11, 12, 14 or 15 as
described in Section 5.8.6. Each PIRQx# line has a separate Route
Control register.
PIRQ[D:A]#
I/OD
In APIC mode, these signals are connected to the internal I/O APIC in
the following fashion: PIRQA# is connected to IRQ16, PIRQB# to
IRQ17, PIRQC# to IRQ18, and PIRQD# to IRQ19. This frees the
legacy interrupts.
PCI Interrupt Requests: In non-APIC mode the PIRQx# signals can
be routed to interrupts 3, 4, 5, 6, 7, 9, 10, 11, 12, 14 or 15 as
described in Section 5.8.6. Each PIRQx# line has a separate Route
Control register.
PIRQ[H:E]# /
GPIO[5:2]
I/OD
In APIC mode, these signals are connected to the internal I/O APIC in
the following fashion: PIRQE# is connected to IRQ20, PIRQF# to
IRQ21, PIRQG# to IRQ22, and PIRQH# to IRQ23. This frees the
legacy interrupts. If not needed for interrupts, these signals can be
used as GPIO.
Datasheet
55
INTEL [ INTEL ]
