Signal Description
2.5
Firmware Hub Interface
Table 2-5.
Firmware Hub Interface Signals
Name
Type
Description
FWH[3:0] /
LAD[3:0]
Firmware Hub Signals. These signals are multiplexed with the LPC
address signals.
I/O
FWH4 /
LFRAME#
Firmware Hub Signals. This signal is multiplexed with the LPC
LFRAME# signal.
O
O
Initialization 3.3 V: This is the identical 3.3 V copy of INIT# intended
for Firmware Hub.
INIT3_3V#
2.6
PCI Interface
Table 2-6.
PCI Interface Signals (Sheet 1 of 3)
Name
Type
Description
PCI Address/Data: AD[31:0] is a multiplexed address and data
bus. During the first clock of a transaction, AD[31:0] contain a
physical address (32 bits). During subsequent clocks, AD[31:0]
contain data. The Intel ICH10will drive all 0s on AD[31:0] during
the address phase of all PCI Special Cycles.
AD[31:0]
I/O
Bus Command and Byte Enables: The command and byte enable
signals are multiplexed on the same PCI pins. During the address
phase of a transaction, C/BE[3:0]# define the bus command.
During the data phase C/BE[3:0]# define the Byte Enables.
C/BE[3:0]# Command Type
0000b
0001b
0010b
0011b
0110b
0111b
1010b
1011b
1100b
1110b
1111b
Interrupt Acknowledge
Special Cycle
I/O Read
I/O Write
C/BE[3:0]#
I/O
Memory Read
Memory Write
Configuration Read
Configuration Write
Memory Read Multiple
Memory Read Line
Memory Write and Invalidate
All command encodings not shown are reserved. The ICH10 does
not decode reserved values, and therefore will not respond if a PCI
master generates a cycle using one of the reserved values.
Device Select: The ICH10 asserts DEVSEL# to claim a PCI
transaction. As an output, the ICH10 asserts DEVSEL# when a PCI
master peripheral attempts an access to an internal ICH10 address
or an address destined for DMI (main memory or graphics). As an
input, DEVSEL# indicates the response to an ICH10-initiated
transaction on the PCI bus. DEVSEL# is tri-stated from the leading
edge of PLTRST#. DEVSEL# remains tri-stated by the ICH10 until
driven by a target device.
DEVSEL#
I/O
50
Datasheet
INTEL [ INTEL ]
