LPC Interface Bridge Registers (D31:F0)
13.1.26 GEN4_DEC—LPC I/F Generic Decode Range 4 Register
(LPC I/F—D31:F0)
Offset Address: 90h – 93h
Attribute:
Size:
Power Well:
R/W
32 bit
Core
Default Value:
00000000h
Bit
Description
31:24
Reserved
Generic I/O Decode Range Address[7:2] Mask — R/W. A 1 in any bit position
indicates that any value in the corresponding address bit in a received cycle will be
treated as a match. The corresponding bit in the Address field, below, is ignored. The
mask is only provided for the lower 6 bits of the DWord address, allowing for decoding
blocks up to 256 bytes in size.
23:18
17:16 Reserved
Generic I/O Decode Range 4 Base Address (GEN4_BASE) — R/W.
NOTE: The ICH Does not provide decode down to the word or byte level.
15:2
1
Reserved
Generic Decode Range 4 Enable (GEN4_EN) — R/W.
0
0 = Disable.
1 = Enable the GEN4 I/O range to be forwarded to the LPC I/F.
13.1.27 LGMR — LPC I/F Generic Memory Range (LPC I/F—
D31:F0) (Corporate Only)
Offset Address: 98h – 9Bh
Attribute:
Size:
Power Well:
R/W
32 bit
Core
Default Value:
00000000h
Bit
Description
Memory Address[31:16] — R/W. This field specifies a 64 KB memory block
anywhere in the 4 GB memory space that will be decoded to LPC as standard LPC
memory cycle if enabled.
31:16
15:1
0
Reserved
LPC Memory Range Decode Enable — R/W. When this bit is set to 1, then the range
specified in bits 31:16 of this register is enabled for decoding to LPC.
Datasheet
403
INTEL [ INTEL ]
