Electrical Characteristics
Figure 8-23. Sleep control signal relationship - Host stays in S5 and Intel Management
Engine boots after G3
t29 8
S LP _S 3#
t297
S 4_S T A T E #
S LP _S 4#
S LP _S 5#
W ake event
t303
S LP _M #
Figure 8-24. S4, S5/M1 to S0/M0
t298
S LP _S 3#
t297
S 4_S T A T E #
S LP _S 4#
S LP _S 5#
W ake event
t303
S LP _M #
NOTE: Vcc includes Vcc1_5_A, Vcc1_5_B, Vcc3_3, Vcc1_1, VccUSBPLL, VccDMIPLL, and
VccSATAPLL.
Figure 8-25. S0 to S3/S4/S5 and G3 Timings
PWROK
Vcc
t294
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Datasheet
291