System Clock Domains
4 System Clock Domains
The Intel® SCH contains many clock frequency domains to support its various
interfaces. Table 7 summarizes these domains.
Table 7.
Intel® SCH Clock Domains
Clock
Domain
Signal Name
Frequency
Source
Usage
H_CLKINP
H_CLKINN
100 MHz or
133 MHz
Used to generate core
and SM internal clocks.
FSB
Main Clock Generator
Main Clock Generator
PCI Express*
PCIE_CLKIN[P:N]
100 MHz
PCI Express ports
Display
Reference
Clock
Primary clock source for
display clocks, USB
controllers, SDIO, HD
Audio
DA_REFCLKIN
96 MHz
Main Clock Generator
DB_REFCLKINSSC
100 MHz
Used by ACPI timer and
the multimedia timers
logic. Stopped during S1
or higher.
CLK14
RTC
CLK14
14.31818 MHz
32.768 kHz
Main Clock Generator
Cyrstal oscillator
RTC, Power Management.
Always running.
RTC_X1, RTC_X2
Derivative Clocks: See Note
Drives SDRAM Ranks 0
and 1. Data Rate is 2x
the clock rate.
SM_CK[1:0]
DDR2
200 MHz or
266 MHz
Intel® SCH
(2x FSB clock)
SM_CK[1:0]#
Intel® SCH
(Multiple of
DA_REFCLKIN)
LA_CLK[P/N]
LVDS, SDVO
100–200 MHz
Display clock outputs
SDVOB_CLK±
Intel® SCH
(¼ FSB clock)
Supplied for external
devices requiring PCICLK
LPC
LPC_CLKOUT[1:0]
N/A
Up to 33 MHz
480 MHz
Intel® SCH
(5x DA_REFCLKIN)
USB2
USB PLL
Intel® SCH
(1/4 DA_REFCLKIN)
Intel HD Audio HDA_CLK
24 MHz
Drives external CODECs
SD/SDIO
MMC
SD[2:0]_CLK
24 MHz
48 MHz
1/4 DA_REFCLKIN
1/2 DA_REFCLKIN
NOTE: These are clock domains that are fractional multiples of existing clock frequencies.
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Datasheet
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