Pin States
Table 5.
Intel® SCH Reset State (Sheet 5 of 5)
Signal Name
WAKE#
Direction
Reset
Post-Reset
S3
S4/S5
I
O
O
O
I
VIX-unknown
VOH
VIX-unknown VIX-unknown
Off
Off
Off
Off
Off
Off
Off
Off
Off
STPCPU#
DPRSLPVR
SLPMODE
RSTWARN
SLPRDY#
RSTRDY#
GPE#
VOH
VOL
VOL
VIH
Off
Off
VOL
VOL
VOH
VIH
VOL
VOL
VIH
O
O
I
VOH
VOH
VOH
VOH
VIX-unknown
High-Z
VIX-unknown VIX-unknown
SLPIOVR#
I/O
High-Z
Off
Real Time Clock
RTC_X1
RTC_X2
I-A
I-A
Running
Running
Running
Running
Running
Running
Running
Running
JTAG
TCK
I
I
pull-up
pull-up
pull-up
High-Z
pull-up
pull-up
pull-up
pull-up
High-Z
pull-up
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
TMS
TDI
I
TDO
TRST#
O
I
Miscellaneous
BSEL2
I
I
VIX-unknown
VIX-unknown
Running
VIH
VIX-unknown
VIX-unknown
Running
VIH
Off
Off
Off
Off
Off
VIH
Off
Off
Off
CFG[1:0]
CLK14
I
Off
INTVRMEN
SPKR
I
VIH
VOL
Off
O
I
VOL
VOL
SMI#,
VIX-unknown
X
VIX-unknown
X
EXTTS
I
Off
GPIO
GPIO[6:0], GPIO[9:8]
GPIOSUS[3:0]
I/O
I/O
High-Z
High-Z
High-Z
High-Z
Off
Off
Off
VIX-unknown
NOTES:
1.
The Intel® SCH power-on is a very controlled sequence with several intermediate
transitional states before the true reset is reached (this is a reset state from PWROK
asserted high to RESET# deasserted high). Pin values are not ensured to be at the
specified reset state until all power supplies and input clocks are stable. The 3.3 V I/O pins
may glitch, toggle or float.
52
Datasheet
INTEL [ INTEL ]
