Intel® HD Audio (D27:F0)
10.2.17 DCKCTL—Docking Control Register
Address Offset:
Default Value:
4Ch
00h
Attribute:
Size:
R/W, RO
8 bits
Default
Bit
and
Description
Access
00h
RO
7:1
Reserved
Dock Attach (DA): Software writes a 1 to this bit to initiate the docking
sequence on the HDA_DOCK_EN# and HDA_DOCKRST# signals. When the
docking sequence is complete, hardware will set the Dock Mated
(GSTS.DM) status bit to a 1.
Software writes a 0 to this bit to initiate the undocking sequence on the
HDA_DOCK_EN# and HDA_DOCKRST# signals. When the undocking
sequence is complete hardware will set the Dock Mated (GSTS.DM) status
bit to a 0.
0
0
R/W, RO
NOTES:
• Software must check the state of the Dock Mated (GSTS.DM) bit prior
to writing to the Dock Attach bit. Software shall only change the DA bit
from a 0 to a 1 when DM=0. Likewise, software shall only change the
DA bit from 1 to 0 when DM=1. If these rules are violated, the results
are undefined.
• This bit is Read Only when the DCKSTS.DS bit = 0.
10.2.18 DCKSTS—Docking Status Register
Address Offset:
Default Value:
4Dh
80h
Attribute:
Size:
R/WO, RO
8 bits
Default
Bit
and
Description
Access
Docking Supported (DS): When set, indicates Intel® SCH supports
docking. DKCTL.DA is only writeable when this bit is 1. This bit is reset on
RESET#, but not on CRST#
1
7
R/WO
00h
RO
6:1
0
Reserved
0
RO
Dock Mated (DM): This bit indicates that codec is physically and
electrically docked.
Datasheet
129
INTEL [ INTEL ]
