Functional Description
Table 10-5. DRAM Address Translation (Dual Channel Symmetric Mode)
Technology (Mb)
Row bits
Column bits
bank bits
256
13
10
2
256
13
9
512
14
10
512
13
10
1024
14
10
1024
13
10
2
2
2
3
3
width (b)
Rows
Columns
Banks
8
16
8192
512
4
8
16
8
16
8192
1024
4
16384
1024
4
8192
1024
4
16384
1024
8
8192
1024
8
Page Size (KB)
Devices per rank
Rank Size (MB)
Depth (M)
Addr bits [n:0]
available in DDR2
Host Address bit
8
8
256
32
27
yes
4
4
128
16
26
yes
8
8
512
64
28
8
4
256
32
27
8
8
1024
128
29
8
4
512
64
28
yes
yes
yes
yes
Memory Address bit
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
r 13
r 11
r 12
r 10
r 9
r 8
r 7
r 6
r 5
r 4
r 3
r 2
r 1
r 0
b 0
b 1
b 2
c 9
c 8
c 7
c 6
c 5
c 4
c 3
h
-
-
-
r 13
r 12
r 10
r 9
r 8
r 7
r 6
r 5
r 4
r 3
r 2
r 1
r 0
r 11
b 1
b 0
c 9
c 8
c 7
c 6
c 5
c 4
c 3
h
-
r 11
r 12
r 10
r 9
r 8
r 7
r 6
r 5
r 4
r 3
r 2
r 1
r 0
b 0
b 1
b 2
c 9
c 8
c 7
c 6
c 5
c 4
c 3
h
r 12
r 10
r 9
r 8
r 7
r 6
r 5
r 4
r 3
r 2
r 1
r 0
r 11
b 1
b 0
c 9
c 8
c 7
c 6
c 5
c 4
c 3
h
-
r 12
r 10
r 9
r 8
r 7
r 6
r 5
r 4
r 3
r 2
r 1
r 0
r 11
b 1
b 0
c 9
c 8
c 7
c 6
c 5
c 4
c 3
h
r 10
r 9
r 8
r 7
r 6
r 5
r 4
r 3
r 2
r 1
r 0
r 11
r 12
b 0
b 1
c 8
c 7
c 6
c 5
c 4
c 3
h
8
7
6
5
c 2
c 1
c 0
c 2
c 1
c 0
c 2
c 1
c 0
c 2
c 1
c 0
c 2
c 1
c 0
c 2
c 1
c 0
4
3
290
Datasheet
INTEL [ INTEL ]
