Functional Description
10.2.4
10.2.5
DRAM Clock Generation
The GMCH generates three differential clock pairs for every supported DIMM. A total of
6 clock pairs are driven directly by the GMCH to 2 DIMMs per channel.
Suspend to RAM and Resume
When entering the Suspend to RAM (STR) state, the SDRAM controller will flush
pending cycles and then enter all SDRAM rows into self refresh. In STR, the CKE
signals remain LOW so the SDRAM devices will perform self-refresh.
10.2.6
DDR2 On-Die Termination
On-die termination (ODT) is a feature that allows a DRAM to turn on/off internal
termination resistance for each DQ, DM, DQS, and DQS# signal for x8 and x16
configurations via the ODT control signals. The ODT feature is designed to improve
signal integrity of the memory channel by allowing the termination resistance for the
DQ, DM, DQS, and DQS# signals to be located inside the DRAM devices themselves
instead of on the motherboard. The GMCH drives out the required ODT signals, based
on memory configuration and which rank is being written to or read from, to the
DRAM devices on a targeted DIMM rank to enable or disable their termination
resistance.
10.3
PCI Express*
See the Section 1.3.4 for list of PCI Express features, and the PCI Express
specification for further details.
This GMCH is part of a PCI Express root complex. This means it connects a host
processor/memory subsystem to a PCI Express hierarchy. The control registers for
this functionality are located in device 1 configuration space and two Root Complex
Register Blocks (RCRBs). The DMI RCRB contains registers for control of the Intel
ICH8 attach ports.
10.3.1
PCI Express* Architecture
The PCI Express architecture is specified in layers. Compatibility with the PCI
addressing model (a load-store architecture with a flat address space) is maintained to
ensure that all existing applications and drivers operate unchanged. The PCI Express
configuration uses standard mechanisms as defined in the PCI Plug-and-Play
specification. The initial speed of 1.25 GHz (250 MHz internally) results in
2.5 Gb/s/direction which provides a 250 MB/s communications channel in each
direction (500 MB/s total) that is close to twice the data rate of classic PCI per lane.
Transaction Layer
The upper layer of the PCI Express architecture is the Transaction Layer. The
Transaction Layer’s primary responsibility is the assembly and disassembly of
Transaction Layer Packets (TLPs). TLPs are used to communicate transactions, such as
read and write, as well as certain types of events. The Transaction Layer also
manages flow control of TLPs.
Datasheet
291
INTEL [ INTEL ]
