Figures
1
2
3
4
5
6
7
8
9
VCC Static and Transient Tolerance............................................................................. 21
VCC Overshoot Example Waveform ............................................................................. 22
Differential Clock Waveform ...................................................................................... 30
Differential Clock Crosspoint Specification ................................................................... 31
Differential Measurements......................................................................................... 31
Differential Clock Waveform ...................................................................................... 33
Differential Clock Crosspoint Specification ................................................................... 33
Processor Package Assembly Sketch........................................................................... 35
Processor Package Drawing Sheet 1 of 3 ..................................................................... 36
10 Processor Package Drawing Sheet 2 of 3 ..................................................................... 37
11 Processor Package Drawing Sheet 3 of 3 ..................................................................... 38
12 Processor Top-Side Marking Example.......................................................................... 40
13 Processor Land Coordinates and Quadrants, Top View................................................... 41
14 land-out Diagram (Top View – Left Side)..................................................................... 44
15 land-out Diagram (Top View – Right Side)................................................................... 45
16 Thermal Profile ........................................................................................................ 77
17 Case Temperature (TC) Measurement Location ............................................................ 78
18 Thermal Monitor 2 Frequency and Voltage Ordering...................................................... 80
19 Processor PECI Topology........................................................................................... 84
20 Conceptual Fan Control on PECI-Based Platforms ......................................................... 85
21 Conceptual Fan Control on Thermal Diode-Based Platforms............................................ 85
22 Processor Low Power State Machine ........................................................................... 88
23 Mechanical Representation of the Boxed Processor ....................................................... 91
24 Space Requirements for the Boxed Processor (Side View).............................................. 92
25 Space Requirements for the Boxed Processor (Top View)............................................... 93
26 Space Requirements for the Boxed Processor (Overall View).......................................... 93
27 Boxed Processor Fan Heatsink Power Cable Connector Description.................................. 94
28 Baseboard Power Header Placement Relative to Processor Socket................................... 95
29 Boxed Processor Fan Heatsink Airspace Keepout Requirements (Top 1 view).................... 96
30 Boxed Processor Fan Heatsink Airspace Keepout Requirements (Side 2 View)................... 96
31 Boxed Processor Fan Heatsink Set Points..................................................................... 97
Tables
1
References.............................................................................................................. 11
2
3
4
5
6
7
8
9
Voltage Identification Definition ................................................................................. 15
Market Segment Selection Truth Table for MSID[1:0] ................................................... 16
Absolute Maximum and Minimum Ratings.................................................................... 18
Voltage and Current Specifications ............................................................................. 19
VCC Static and Transient Tolerance............................................................................. 20
V
CC Overshoot Specifications ..................................................................................... 21
FSB Signal Groups ................................................................................................... 23
Signal Characteristics ............................................................................................... 24
10 Signal Reference Voltages......................................................................................... 24
11 GTL+ Signal Group DC Specifications.......................................................................... 25
12 Open Drain and TAP Output Signal Group DC Specifications........................................... 25
13 CMOS Signal Group DC Specifications......................................................................... 26
14 GTL+ Bus Voltage Definitions .................................................................................... 27
15 Core Frequency to FSB Multiplier Configuration ............................................................ 28
16 BSEL[2:0] Frequency Table for BCLK[1:0]................................................................... 29
17 Front Side Bus Differential BCLK Specifications............................................................. 30
18 Front Side Bus Differential BCLK Specifications............................................................. 32
19 PECI DC Electrical Limits........................................................................................... 34
20 Processor Loading Specifications ................................................................................ 39
Datasheet
5
INTEL [ INTEL ]
