Electrical Specifications
2.7.8
BCLK[1:0] Specifications (CK505 based Platforms)
Table 2-18. Front Side Bus Differential BCLK Specifications
1
Symbol
Parameter
Input Low Voltage
Min
Typ
Max
Unit
Figure
Notes
2
2
V
-0.30
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
1.2
N/A
1.15
0.550
0.140
1.4
V
V
2-4
2-4
L
V
Input High Voltage
Absolute Crossing Point
Range of Crossing Points
Overshoot
H
3, 4,
5
V
0.300
N/A
V
2-4, 2-5
2-4, 2-5
2-4
CROSS(abs)
4
6
6
7
ΔV
V
CROSS
V
N/A
V
OS
US
V
Undershoot
-0.300
0.300
-5
N/A
V
2-4
V
Differential Output Swing
Input Leakage Current
Pad Capacitance
N/A
V
2-6
SWING
I
5
μA
pF
LI
8
Cpad
.95
1.45
Notes:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. "Steady state" voltage, not including overshoot or undershoot.
3. Crossing voltage is defined as the instantaneous voltage value when the rising edge of BCLK0 equals the falling
edge of BCLK1.
4. V
is the statistical average of the V measured by the oscilloscope.
Havg
H
5. The crossing point must meet the absolute and relative crossing point specifications simultaneously.
6. Overshoot is defined as the absolute value of the maximum voltage. Undershoot is defined as the absolute
value of the minimum voltage.
7. Measurement taken from differential waveform.
8. Cpad includes die capacitance only. No package parasitics are included.
Figure 2-4. Differential Clock Waveform
CLK 0
VCROSS Max
550 mV
VCROSS
Median + 75 mV
VCROSS
VCROSS
median
median
VCROSS
VCROSS Min
300 mV
Median - 75 mV
CLK 1
High Time
Low Time
Period
Dual-Core Intel® Xeon® Processor 3000 Series Datasheet
31
INTEL [ INTEL ]
