Electrical Specifications
2.7.3.1
GTL+ Front Side Bus Specifications
In most cases, termination resistors are not required as these are integrated into the
processor silicon. See Table 2-9 for details on which GTL+ signals do not include on-die
termination.
Valid high and low levels are determined by the input buffers by comparing with a
reference voltage called GTLREF. Table 2-15 lists the GTLREF specifications. The GTL+
reference voltage (GTLREF) should be generated on the system board using high
precision voltage divider circuits.
Table 2-15. GTL+ Bus Voltage Definitions
1
Symbol
Parameter
Min
Typ
Max
Units
Notes
2
GTLREF_PU
GTLREF pull up resistor on
Mukilteo-2 (3000/3010) chipset
family boards
124 * 0.99
124
124 * 1.01
Ω
2
GTLREF_PD
GTLREF pull down resistor on
Mukilteo-2 (3000/3010) chipset
family boards
210 * 0.99
210
210 * 1.01
Ω
2
2
GTLREF_PU
GTLREF_PD
GTLREF pull up resistor on
100 * 0.99
200 * 0.99
100
200
100 * 1.01
200 * 1.01
Ω
Ω
Bearlake chipset family boards
GTLREF pull down resistor on
Bearlake chipset family boards
3
4
4
R
Termination Resistance
COMP Resistance
45
50
55
Ω
Ω
Ω
TT
COMP[3:0]
COMP8
49.40
24.65
49.90
24.90
50.40
25.15
COMP Resistance
Notes:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. GTLREF is to be generated from V by a voltage divider of 1% resistors (one divider for each GTLEREF land).
TT
Refer to the applicable platform design guide for implementation details.
3. R is the on-die termination resistance measured at V /3 of the GTL+ output driver. Refer to the appropriate
TT
TT
platform design guide for the board impedance. Refer to processor I/O buffer models for I/V characteristics.
4. COMP resistance must be provided on the system board with 1% resistors. See the applicable platform design
guide for implementation details. COMP[3:0] and COMP8 resistors are to V
.
SS
2.7.4
2.7.5
Clock Specifications
Front Side Bus Clock (BCLK[1:0]) and Processor Clocking
BCLK[1:0] directly controls the FSB interface speed as well as the core frequency of the
processor. As in previous generation processors, the processor’s core frequency is a
multiple of the BCLK[1:0] frequency. The processor bus ratio multiplier will be set at its
default ratio during manufacturing. Refer to Table 2-16 for the processor supported
ratios.
The processor uses a differential clocking implementation. For more information on the
processor clocking, contact your Intel Field representative. Platforms using a CK505
Clock Synthesizer/Driver should comply with the specifications in Section 2.7.8.
Platforms using a CK410 Clock Synthesizer/Driver should comply with the specifications
in Section 2.7.9.
Dual-Core Intel® Xeon® Processor 3000 Series Datasheet
29
INTEL [ INTEL ]
