Electrical Specifications
Table 2-16. Core Frequency to FSB Multiplier Configuration
Multiplication of
System Core
Frequency to FSB
Frequency
Core Frequency
Core Frequency
(266 MHz
BCLK/1066 MHz FSB)
(333 MHz
BCLK/1333 MHz
FSB)
1, 2
Notes
1/6
1/7
1.60 GHz
1.87 GHz
2.13 GHz
2.40 GHz
2.66 GHz
2.93 GHz
2.00 GHz
2.33 GHz
2.66 GHz
3.00 GHz
na
-
-
-
-
-
-
1/8
1/9
1/10
1/11
na
Notes:
1. Individual processors operate only at or below the rated frequency.
2. Listed frequencies are not necessarily committed production frequencies.
2.7.6
FSB Frequency Select Signals (BSEL[2:0])
The BSEL[2:0] signals are used to select the frequency of the processor input clock
(BCLK[1:0]). Table 2-17 defines the possible combinations of the signals and the
frequency associated with each combination. The required frequency is determined by
the processor, chipset, and clock synthesizer. All agents must operate at the same
frequency.
The Dual-Core Intel® Xeon® processor 3000 series operates at a 1066 MHz FSB
frequency (selected by a 266 MHz BCLK[1:0] frequency).
Table 2-17. BSEL[2:0] Frequency Table for BCLK[1:0]
BSEL2
BSEL1
BSEL0
FSB Frequency
L
L
L
L
L
H
H
L
266 MHz
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
333 MHz
L
H
H
H
H
L
L
H
H
H
H
L
H
H
L
L
2.7.7
Phase Lock Loop (PLL) and Filter
An on-die PLL filter solution will be implemented on the processor. The VCCPLL input is
used for the PLL. Refer to Table 2-4 for DC specifications.
30
Dual-Core Intel® Xeon® Processor 3000 Series Datasheet
INTEL [ INTEL ]
