Electrical Specifications
2.7.2
2.7.3
CMOS and Open Drain Signals
Legacy input signals such as A20M#, IGNNE#, INIT#, SMI#, and STPCLK# use CMOS
input buffers. All of the CMOS and Open Drain signals are required to be asserted/de-
asserted for at least four BCLKs in order for the processor to recognize the proper
signal state. See Section 2.7.3 for the DC. See Section 6.2 for additional timing
requirements for entering and leaving the low power states.
Processor DC Specifications
The processor DC specifications in this section are defined at the processor core (pads)
unless otherwise stated. All specifications apply to all frequencies and cache sizes
unless otherwise stated.
Table 2-11. GTL+ Signal Group DC Specifications
1
Symbol
Parameter
Min
Max
Unit
Notes
2,
3
V
Input Low Voltage
Input High Voltage
Output High Voltage
Output Low Current
-0.10
GTLREF – 0.10
V
V
V
A
IL
4, 5,
5, 3
3
V
GTLREF + 0.10
V
+ 0.10
TT
IH
V
V
– 0.10
V
OH
OL
TT
TT
I
N/A
V
/[(R
)+(2*R
-
TT_MAX
TT_MIN
MIN
ON_
)]
6
7
I
Input Leakage Current
Output Leakage Current
Buffer On Resistance
N/A
N/A
10
± 100
± 100
13
µA
µA
Ω
LI
I
LO
R
ON
Notes:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. V is defined as the voltage range at a receiving agent that will be interpreted as a logical low value.
IL
3. The V referred to in these specifications is the instantaneous V
.
TT
TT
4. V is defined as the voltage range at a receiving agent that will be interpreted as a logical high value.
IH
IH
5. V and V
may experience excursions above V .
SS
TT
OH
TT
6. Leakage to V with land held at V
7. Leakage to V with land held at 300 mV.
.
TT
.
Table 2-12. Open Drain and TAP Output Signal Group DC Specifications
1
Symbol
Parameter
Min
Max
Unit
Notes
V
Output Low Voltage
0
0.20
V
-
OL
VTT
0.05
–
VTT +
0.05
2
VOH
Output High Voltage
V
3
4
I
I
Output Low Current
16
50
mA
µA
OL
LO
Output Leakage Current
N/A
± 200
Notes:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. V is determined by the value of the external pull-up resister to V . Refer to theappropriate platform design
OH
TT
guide for details.
3. Measured at V * 0.2.
TT
4. For Vin between 0 and V
.
OH
Dual-Core Intel® Xeon® Processor 3000 Series Datasheet
27
INTEL [ INTEL ]
