Errors
6.1.4
Other Errors
Table 6-5.
Other Errors
Error
Response
Overtemp - Temp > TEMPHI and overtemp If OVERTEMP error type enabled in EMASK Register
enabled
1.
2.
The OVERTEMP bit will be set in the FERR or NERR register as appropriate
Error/Alert Asserted bit set in FBD Status 0 register
If TEMPHIENABLE set in TEMPSTAT register also
3.
Shut down DDR channel:
•
Drive CKE low to the DRAMs and float the command, address, and data signals.
CKE, ODT, and clock continue to be driven. The clocks to the DRAMS may be
stopped after the CKE has been registered low
4.
5.
The FBD interface goes to electrical idle, with the receivers shut off to reduce
power.
The core will continue to be clocked, and the AMB will respond to SMBus
commands. This allows the host controller to determine the error condition
Note: No recovery expected, just trying to prevent Si meltdown
The AMB will remain in this state until the temperature is below TEMPHI and the
OVERTEMP bit is reset via SMBus or a hardware reset.
Else ignore error
Note: A hardware reset will place the TEMPHIENABLE bit in its default state of
disabled.
Injected alert
If INJCRC error type enabled in EMASK Register
1.
2.
3.
4.
5.
No command executed
120 bit Raw SB Frame captured in RECFBD Error Log Registers
Type of error logged in FERR/NERR registers
Error/Alert Asserted bit set in FBD Status 0 register
Ignore future commands except Soft Channel Reset until Soft Channel Reset or
Link Reset Received
6.
Alert Frame sent continuously starting with NB frame in which returned data
pattern would be sent if aborted command had been a config read. Alert
patterns continue until Soft Channel Reset or Link Fast Reset received.
Else ignore error
NOTE: this basically the same as a CRC error except that CRC is not actually
corrupted
Injected error
No REFCLK
If INJERR error type enabled in EMASK Register
1.
2.
Type of error logged in FERR/NERR registers
Error/Alert Asserted bit set in FBD Status 0 register
Else ignore error
Reset should not be released if no REFCLK present.PLL will not achieve lock, the
AMB will not come out of reset.
6.2
Error Logging
6.2.1
Error Logging Procedure
There are three basic types of errors in FBD: OverTemp, Alerts and Status Only
Errors.The first occurrence of any type of unmasked error are flagged in the FERR
register. Multiple bits can be set in this register if multiple errors occur in the same
clock period. Subsequent errors are flagged in the NERR register.
Unmasked “Alert” errors generate in-band link alert messages. All unmasked errors
also set the error bit in FBDS0 that is returned in regularly scheduled in-band status
response messages that occur following Sync commands.
There are error data logs associated with some of the errors. Once the first “Alert” error
has been flagged in the FERR or NERR (and matching SB frame data logged), the log
registers for that error remain locked until either 1) all “Alert” error bits in the FERR
and/or NERR are cleared, or 2) a power-up reset. Once the first Unimplemented
74
Intel® 6400/6402 Advanced Memory Buffer Datasheet
INTEL [ INTEL ]
