SMBus Interface
• For repeaters or LAI AMBs:
— Slave Address[6:3] = 4’b0011
— Slave Address[2:0] = SA[2:0]
Each SMBus transaction has an 8-bit command driven by the master. The format for
this command is illustrated in Table 7-1 below.
Table 7-1.
SMBus Command Encoding
7
6
5
4
3:2
1:0
Internal Command:
SMBus Command:
00 - Read DWord
01 - Write Byte
10 - Write Word
11 - Write DWord
00 - Byte
01 - Word
10 - Block
11 - Rsvd
Begin
End
Rsvd
PEC_en
The Begin bit indicates the first transaction of a read or write sequence.
The End bit indicates the last transaction of a read or write sequence.
The PEC_en bit enables the 8-bit PEC generation and checking logic.
The Internal Command field specifies the internal command to be issued by the SMBus
slave logic. Note that the Internal Command must remain consistent (that is, not
change) during a sequence that accesses a configuration register. Operation cannot be
guaranteed if it is not consistent when the command setup sequence is done.
The SMBus Command field specifies the SMBus command to be issued on the bus. This
field is used as an indication of the length of transfer so the slave knows when to
expect the PEC packet (if enabled).
Reserved bits should be written to zero to preserve future compatibility.
7.1.3
FBD AMB Register Access Protocols
Sequences of these basic commands will initiate internal accesses to the component’s
configuration registers.
Each configuration read or write first consists of an SMBus write sequence which
initializes the register’s address. The term sequence is used since these variables may
be written with a single block write or multiple word or byte writes. Once these
parameters are initialized, the SMBus master can initiate a read sequence (which
performs a configuration read) or a write sequence (which performs a configuration
write).
Table 7-2.
SMBus Protocol Addressing Fields
Address Field
Bits
Description
Name
Reserved
7:0
4:0
2:0
7:0
7:0
Reserved - AMB may alias all these addresses to 00h
Reserved - AMB may alias all these addresses to 00h
Function Address
Dev
Function
Reg_Num[15:8]
Reg_Num[7:0]
Reserved - AMB may alias all these addresses to 00h
Register Address within Function
78
Intel® 6400/6402 Advanced Memory Buffer Datasheet
INTEL [ INTEL ]
