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313072-002 参数 Datasheet PDF下载

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型号: 313072-002
PDF下载: 下载PDF文件 查看货源
内容描述: 高级内存缓冲器 [Advanced Memory Buffer]
分类和应用:
文件页数/大小: 250 页 / 3863 K
品牌: INTEL [ INTEL ]
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Errors  
Table 6-2.  
Link Errors in Normal Operation (Sheet 2 of 2)  
Error  
Response  
Access to unimplemented register  
If UNIMPLCFG error type enabled in EMASK Register  
1.  
2.  
3.  
Drop Config Write cmds  
Capture Addr in RECCFG register if not previously set  
Return 0’s data if Config Read (or return -1 if Read addr to unimplemented  
function - though currently expect all functions to be used)  
UNIMPLCFG error type logged in FERR or NERR registers  
Error/Alert Asserted bit set in FBD Status 0 register  
4.  
5.  
Else ignore error  
NOTE: The timing of the Error/Alert Asserted bit in FBD Status 0 response for an  
unimplemented register is not guaranteed relative to the corresponding Sync/Status  
boundaries. For example, if an unimplemented register access occurs in the frame  
before a Sync frame, the Error Asserted bit in FBD Status 0 may not be asserted in  
northbound Status corresponding to that Sync. But it will be asserted in a later  
Status response.  
Undefined command  
Undefined commands with good CRC are ignored. This is not considered an error  
condition, and is not logged. Treat as reserved command or Channel NOP  
TID error on config writes  
If the TID bit on a config write matches the value of the previous TID bit, the write  
is ignored. The TID bit stored in the AMB is left unchanged in this case.  
This error does not cause an alert frame, and is not logged.  
The purpose of the TID bit is to allow the host to retry a config write command  
following a fast reset if it does not know if it had been executed prior to an alert. If  
the config write had occurred the TID bit will be the same, the retried write will be  
ignored. If it had not occurred, the TID bit will be opposite, and the retried write to  
will be executed.  
6.1.2  
DDR Errors  
Table 6-3.  
DDR Errors  
Error  
Response  
Failure of software to achieve calibration  
DDR voltage does not power up  
This is detected through firmware during the calibration routine.  
Firmware should treat the DIMM as a repeater if it is an intermediate DIMM or map  
it out if it is the last DIMM in the chain  
if normal FBD interface comes up, should at least act like a repeater. Does not bring  
down FBD channel - like above. DDR cmds directed at DIMM will fail to return valid  
responses.  
6.1.3  
Host Protocol Errors  
AMBs are not expected to detect bad protocol from the host.  
Table 6-4.  
Host Protocol Errors  
Error  
Response  
Illegal combinations of commands  
AMB response to illegal command combinations is undefined  
see Concurrent Command Delivery  
Rules section of the FBD Architecture  
and Protocol Specification  
Commands to multiple AMBs to return  
data in the same return frame.  
If multiple AMBs attempt to return data in the same frame, the host will see the  
data from the northern most AMB which is providing data, as it will replace any data  
sent from AMBs to its south. A host controller should not produce commands which  
would cause multiple AMBs to respond with data in the same frame. A special case  
can occur where Alert frames are being sent by one or more AMBs while another  
AMB is returning data from a command. These cases are discussed in the  
Architecture and Protocol spec in the Northbound Alert Frame section.  
Intel® 6400/6402 Advanced Memory Buffer Datasheet  
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