Debug and Logic Analyzer Mode
5.1.9
LAI Block Diagram
Figure 5-9 is a block diagram of the LAI implementation.
The LAI block defines a frame from the host (not the AMB) point-of-view, so the slota
command is delayed by one core cycle relative to the slotb and slotc commands. The
southbound delay pipeline consists of one set of core registers for slota, and one set of
core registers for delayed slota, and slotb and slotc.
The protocol unwrapping and pattern recognition block takes the registered
southbound frame and detects and logs any local events. Events are selected in this
same cycle, registered on the core clock, and then forwarded to the DDR cluster. The
southbound frame is also registered once more and forwarded to the DDR cluster.
The northbound registers the line this data to the same clock domain as the
southbound data before it is forwarded to the DDR cluster.
Figure 5-9. Block Diagram of AMB in LAI Mode
AMB in LAI Mode
Remainder of path unmodified*
Southbound In
Reference clock
Southbound Out
S[59:00]
Retiming
Southbound
Delay
Q
Demux
Deskew
Registers
SMB
Protocol
&Pattern
CLK[p,n]
QUAL
Recognition
Q
Q
FRAME
Events
Selection,
&
EV[3:0]
Responses
TRIG[10:0]
Q
Q
MODE
Control/Status
Register
N[83:00]
Northbound
Delay
Q
Demux
Deskew
Registers
Northbound Out
Remainder of path unmodified*
Northbound In
Retiming &
Merge*
Intel® 6400/6402 Advanced Memory Buffer Datasheet
67
INTEL [ INTEL ]
