Debug and Logic Analyzer Mode
Table 5-1.
DDR Pins Shared With LAI Functionality
Use in LAI
Mode
Signal Type
Count
Speed (MHz)
Comment
DDR
DDR DQ & DQS
DDR Cmd/Addr
108
533/667
266/333
~ LAI signal
~ LAI signal
DQS must run single ended in LAI
mode
56
Most must run double speed in LAI
mode
Some may be dedicated to
bidirectional Event Bus
Clocks to DRAMs
8
533/667
analog
~ LAI signal
May run single ended in LAI mode
Not suitable for LAI signals
DDR Comp and analog
5
177
Total DDR Pins
Table 5-2.
List of Pins Required to Enable Debug With LAI Functionality
Signal Type
Southbound
Count
Speed (MHz)
Comment
S[59:0]
60
533/667
Data
Data
Northbound
N[83:0]
MODE
84
1
533/667
267/333
267/333
267/333
533/667
533/667
100
TRIG[10:0]
CLK
11
4
Two Differential pairs
QUAL
1
FRAME
1
EV[3:0]
Comp Pins
4
Bidirectional
5
Analog
Required for signal integrity
171
Total Pins
5.1.4
LAI Mode Signal Definitions
Table 5-3.
LAI Mode Added Signals (Sheet 1 of 2)
Signal Type
S[59:0]
Direction
Out
Definition
Southbound demuxed (6x10) traffic
Northbound demuxed (6x14) traffic
Link mode:
N[83:0]
MODE
Out
Out
0 = after training complete
1 = before training complete
TRIG[10:0]
Out
Triggers to LA. This provides eleven unique trigger signals to the
LA from the AMB LAI as a result of frame pattern matching, state
matching, and/or cross-triggering events from other LAIs. This
allows cooperating AMB LAIs to overcome (a) limitations of LA in
recognizing serial traffic patterns that exceed LA pattern
matching capabilities and, (b) relatively long latencies in cross-
triggering between LA modules.
56
Intel® 6400/6402 Advanced Memory Buffer Datasheet
INTEL [ INTEL ]
