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300 参数 Datasheet PDF下载

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型号: 300
PDF下载: 下载PDF文件 查看货源
内容描述: 赛扬D处理器 [Celeron D Processor]
分类和应用:
文件页数/大小: 95 页 / 2070 K
品牌: INTEL [ INTEL ]
 浏览型号300的Datasheet PDF文件第63页浏览型号300的Datasheet PDF文件第64页浏览型号300的Datasheet PDF文件第65页浏览型号300的Datasheet PDF文件第66页浏览型号300的Datasheet PDF文件第68页浏览型号300的Datasheet PDF文件第69页浏览型号300的Datasheet PDF文件第70页浏览型号300的Datasheet PDF文件第71页  
Land Listing and Signal Descriptions  
Table 25.  
Signal Description (Sheet 1 of 9)  
Name  
Type  
Description  
DBR# (Debug Reset) is used only in processor systems where no  
debug port is implemented on the system board. DBR# is used by a  
DBR#  
Output debug port interposer so that an in-target probe can drive system  
reset. If a debug port is implemented in the system, DBR# is a no  
connect in the system. DBR# is not a processor signal.  
DBSY# (Data Bus Busy) is asserted by the agent responsible for  
driving data on the processor FSB to indicate that the data bus is in  
use. The data bus is released after DBSY# is de-asserted. This  
signal must connect the appropriate pins/lands on all processor FSB  
Input/  
Output  
DBSY#  
agents.  
DEFER# is asserted by an agent to indicate that a transaction  
cannot be ensured in-order completion. Assertion of DEFER# is  
Input normally the responsibility of the addressed memory or input/output  
agent. This signal must connect the appropriate pins/lands of all  
processor FSB agents.  
DEFER#  
DP[3:0]#  
DRDY#  
DP[3:0]# (Data parity) provide parity protection for the D[63:0]#  
Input/ signals. They are driven by the agent responsible for driving  
Output D[63:0]#, and must connect the appropriate pins/lands of all  
processor FSB agents.  
DRDY# (Data Ready) is asserted by the data driver on each data  
transfer, indicating valid data on the data bus. In a multi-common  
Input/  
clock data transfer, DRDY# may be de-asserted to insert idle clocks.  
Output  
This signal must connect the appropriate pins/lands of all processor  
FSB agents.  
DSTBN[3:0]# are the data strobes used to latch in D[63:0]#.  
Signals  
Associated Strobe  
D[15:0]#, DBI0#  
D[31:16]#, DBI1#  
D[47:32]#, DBI2#  
D[63:48]#, DBI3#  
DSTBN0#  
DSTBN1#  
DSTBN2#  
DSTBN3#  
Input/  
Output  
DSTBN[3:0]#  
DSTBP[3:0]# are the data strobes used to latch in D[63:0]#.  
Signals  
Associated Strobe  
D[15:0]#, DBI0#  
D[31:16]#, DBI1#  
D[47:32]#, DBI2#  
D[63:48]#, DBI3#  
DSTBP0#  
DSTBP1#  
DSTBP2#  
DSTBP3#  
Input/  
Output  
DSTBP[3:0]#  
FC signals are signals that are available for compatibility with other  
processors.  
FCx  
Other  
Datasheet  
67  
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