Land Listing and Signal Descriptions
4.2
Alphabetical Signals Reference
Table 25.
Signal Description (Sheet 1 of 9)
Name
Type
Description
A[35:3]# (Address) define a 236-byte physical memory address
space. In sub-phase 1 of the address phase, these signals transmit
the address of a transaction. In sub-phase 2, these signals transmit
transaction type information. These signals must connect the
appropriate pins/lands of all agents on the processor FSB. A[35:3]#
are protected by parity signals AP[1:0]#. A[35:3]# are source
synchronous signals and are latched into the receiving buffers by
ADSTB[1:0]#.
Input/
Output
A[35:3]#
On the active-to-inactive transition of RESET#, the processor
samples a subset of the A[35:3]# signals to determine power-on
configuration. See Section 6.1 for more details.
If A20M# (Address-20 Mask) is asserted, the processor masks
physical address bit 20 (A20#) before looking up a line in any
internal cache and before driving a read/write transaction on the
bus. Asserting A20M# emulates the 8086 processor's address wrap-
around at the 1-MB boundary. Assertion of A20M# is only supported
in real mode.
A20M#
Input
A20M# is an asynchronous signal. However, to ensure recognition of
this signal following an Input/Output write instruction, it must be
valid along with the TRDY# assertion of the corresponding Input/
Output Write bus transaction.
ADS# (Address Strobe) is asserted to indicate the validity of the
transaction address on the A[35:3]# and REQ[4:0]# signals. All bus
agents observe the ADS# activation to begin parity checking,
protocol checking, address decode, internal snoop, or deferred reply
ID match operations associated with the new transaction.
Input/
Output
ADS#
Address strobes are used to latch A[35:3]# and REQ[4:0]# on their
rising and falling edges. Strobes are associated with signals as
shown below.
Input/
Output
Signals
Associated Strobe
ADSTB[1:0]#
REQ[4:0]#, A[16:3]#
A[35:17]#
ADSTB0#
ADSTB1#
AP[1:0]# (Address Parity) are driven by the request initiator along
with ADS#, A[35:3]#, and the transaction type on the REQ[4:0]#.
A correct parity signal is high if an even number of covered signals
are low and low if an odd number of covered signals are low. This
allows parity to be high when all the covered signals are high.
AP[1:0]# should connect the appropriate pins/lands of all processor
FSB agents. The following table defines the coverage model of these
signals.
Input/
Output
AP[1:0]#
Request Signals
Subphase 1
Subphase 2
A[35:24]#
A[23:3]#
AP0#
AP1#
AP1#
AP1#
AP0#
AP0#
REQ[4:0]#
64
Datasheet
INTEL [ INTEL ]
