Intel® Celeron® Processor for PGA370 up to 1.40 GHz on 0.13 µ Process
Table 29. Signal Ringback Specifications for Non-AGTL Signal Simulation at the Processor
Pins
Maximum Ringback
Input Signal Group
Non-AGTL Signals 2
Non-AGTL Signals 2
Transition
(with Input Diodes Present)
Unit
Figure
0 → 1
1 → 0
0 → 1
Vcmos_ref + 0.200
Vcmos_ref - 0.300
1.44
V
V
V
21
21
21
PWRGOOD
NOTES:
1. Unless otherwise noted, all specifications in this table apply to the processor up to 1.40 GHz frequency.
2. Non-AGTL signals except PWRGOOD.
3.3.3
Settling Limit Guideline
Settling limit defines the maximum amount of ringing at the receiving pin that a signal must reach
before its next transition. The amount allowed is 10% of the total signal swing (VHI –V ) above
LO
and below its final value. A signal should be within the settling limits of its final value, when either
in its high state or low state, before it transitions again.
Signals that are not within their settling limit before transitioning are at risk of unwanted
oscillations which could jeopardize signal integrity. Simulations to verify settling limit may be
done either with or without the input protection diodes present. Violation of the settling limit
guideline is acceptable if simulations of 5 to 10 successive transitions do not show the amplitude of
the ringing increasing in the subsequent transitions.
3.4
VTT_PWRGD Signal Quality Specification
The VTT_PWRGD signal is an input to the processor used to determine that the VTT power is
stable and the VID and BSEL signals should be driven to their final state by the processor. To
ensure the processor correctly reads this signal, it must meet the following requirement while the
signal is in its transition region of 300 mV to 900 mV. Also, VTT_PWRGD should only enter the
transition region once, after VTT is at nominal values, for the assertion of the signal.
Amount of noise (glitch) < 100 mV
In addition, the VTT_PWRGD signal should have a reasonable transition time through the
transition region. A sharp edge on the signal transition will minimize the chance of noise causing a
glitch on this signal. Intel recommends the following transition time for the VTT_PWRGD signal.
Transition time (300 mV to 900 mV) ≤ 100 us
3.4.1
Transition region
The transition region covered by this requirement is 300 mV to 900 mV. Once the VTT_PWRGD
signal is in that voltage range, the processor is more sensitive to noise which may be present on the
signal. The transition region when the signal first crosses the 300 mV voltage level and continues
until the last time it is below 900 mV.
Datasheet
49
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