E
1.0
INTRODUCTION
This datasheet contains 8- and 16-Mbit Fast Boot
Block memory information. Section 1.0 provides a
flash memory overview. Sections 2.0 through 8.0
describe the memory functionality and electrical
specifications for extended and automotive
temperature product offerings.
FAST BOOT BLOCK DATASHEET
block erase and program operations at 2.7 V
(3.3 V for automotive temperature) and 12 V V
PP
.
The 12 V V
PP
option renders the fastest program
performance to increase factory programming
throughput. With the 2.7 V (3.3 V for automotive
temperature) V
PP
option, V
CC
and V
PP
can be tied
together for a simple, low power design. In addition
to the voltage flexibility, the dedicated V
PP
pin gives
complete data protection when V
PP
≤
V
PPLK
.
The flexible input/output (I/O) voltage capability
helps reduce system power consumption and
simplify interfacing to sub 2.7 V and 5 V CPUs.
Powered by V
CCQ
pins, the I/O buffers can operate
at a lower voltage than the flash memory core. With
V
CCQ
voltage at 1.65 V, the I/Os swing between
GND and 1.65 V, reducing I/O power consumption
by 65% over standard 3 V flash memory
components. The low voltage and 5 V-safe feature
also helps ease CPU interfacing by adapting to the
CPU’s bus voltage.
The device’s Command User Interface (CUI) serves
as the interface between the system processor and
internal flash memory operation. A valid command
sequence written to the CUI initiates device
automation. This automation is controlled by an
internal Write State Machine (WSM) which
automatically executes the algorithms and timings
necessary for block erase and program operations.
The status register provides WSM feedback by
signifying block erase or program completion and
status.
Block erase and program automation allows erase
and program operations to be executed using an
industry-standard two-write command sequence. A
block erase operation erases one block at a time,
and data is programmed in word increments. Erase
suspend allows system software to suspend an
ongoing block erase operation in order to read from
or program data to any other block. Program
suspend allows system software to suspend an
ongoing program operation in order to read from
any other location.
Fast Boot Block flash memory devices offer two low
power savings features: Automatic Power Savings
(APS) and standby mode. The device automatically
enters APS mode following the completion of a read
cycle. Standby mode is initiated when the system
deselects the device by driving CE# inactive or
RST# active. RST# also resets the device to read
array, provides write protection, and clears the
status register. Combined, these two features
significantly reduce power consumption.
5
1.2
Product Overview
The Fast Boot Block flash memory family provides
density upgrades with pinout compatibility for 8- and
16-Mbit densities. This family of products are high
performance, low voltage memories with a 16-bit
data bus and individually erasable blocks. These
blocks are optimally sized for code and data
storage. Eight 4-Kword parameter blocks are
positioned at either the top (denoted by -T suffix) or
bottom (denoted by -B suffix) of the address map.
The rest of the device is grouped into
32-Kword main blocks. The upper two (or lower
two) parameter and all main blocks can be locked
for complete code protection.
The device’s optimized architecture and interface
dramatically increases read performance beyond
previously
attainable
levels.
It
supports
asynchronous page-mode and synchronous burst
reads from main blocks (parameter blocks support
single asynchronous and synchronous reads).
Upon initial power-up or return from reset, the
device defaults to a page-mode read configuration.
Page-mode read configuration is ideal for non-clock
memory systems and is compatible with page-
mode ROM. Synchronous burst reads are enabled
by writing to the read configuration register. In
synchronous burst mode, the CLK input increments
an internal burst address generator, synchronizes
the flash memory with the host CPU, and outputs
data on every rising (or falling) CLK edge up to
54 MHz (25 MHz for automotive temperature). An
output signal, WAIT#, is also provided to ease CPU
to
flash
memory
communication
and
synchronization during continuous burst operations.
In addition to the enhanced architecture and
interface, this family of products incorporates
SmartVoltage technology which enables fast factory
programming and low power designs. Specifically
designed for low voltage systems, Fast Boot Block
flash memory components support read operations
at 2.7 V (3.3 V for automotive temperature) V
CC
and
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