Intel StrataFlash® Wireless Memory (L18)
Figure 31.
Operating Mode with Correct Command Sequence Example
Address [A]
WE# [W]
Partition A
Partition B
Partition A
OE# [G]
Data [D/Q]
0x20
Valid Array Data
0xD0
Figure 32.
Operating Mode with Illegal Command Sequence Example
Address [A]
WE# [W]
Partition A
Partition B
Partition A
Partition A
OE# [G]
Data [D/Q]
0x20
0xFF
0xD0
SR[7:0]
14.2.1
Simultaneous Operation Details
The Intel StrataFlash® Wireless Memory (L18) supports simultaneous read from one partition
while programming or erasing in any other partition. Certain features like the Protection Registers
and Query data have special requirements with respect to simultaneous operation capability. These
will be detailed in the following sections.
14.2.2
Synchronous and Asynchronous RWW Characteristics and
Waveforms
This section describes the transition of write operation to asynchronous read, write to synchronous
read, and write operation with clock active.
14.2.2.1
Write operation to asynchronous read transition
W18 - tWHAV
The AC parameter W18 (tWHAV-WE# High to Address Valid) is required when transitioning from a
write cycle (WE# going high) to perform an asynchronous read (only address valid is required).
April 2005
72
Intel StrataFlash® Wireless Memory (L18)
Order Number: 251902, Revision: 009
Datasheet
INTEL [ INTEL ]
