Intel StrataFlash® Wireless Memory (L18)
If a block is locked or locked-down during an erase suspend of the same block, the lock status bits
change immediately. However, the erase operation completes when it is resumed. Block lock
operations cannot occur during a program suspend. See Appendix A, “Write State Machine
(WSM)” on page 78, which shows valid commands during an erase suspend.
13.2
Protection Registers
The device contains 17 Protection Registers (PRs) that can be used to implement system security
measures and/or device identification. Each Protection Register can be individually locked.
The first 128-bit Protection Register is comprised of two 64-bit (8-word) segments. The lower 64-
bit segment is pre-programmed at the factory with a unique 64-bit number. The other 64-bit
segment, as well as the other sixteen 128-bit Protection Registers, are blank. Users can program
these registers as needed. When programmed, users can then lock the Protection Register(s) to
prevent additional bit programming (see Figure 29, “Protection Register Map” on page 69).
The user-programmable Protection Registers contain one-time programmable (OTP) bits; when
programmed, register bits cannot be erased. Each Protection Register can be accessed multiple
times to program individual bits, as long as the register remains unlocked.
Each Protection Register has an associated Lock Register bit. When a Lock Register bit is
programmed, the associated Protection Register can only be read; it can no longer be programmed.
Additionally, because the Lock Register bits themselves are OTP, when programmed, Lock
Register bits cannot be erased. Therefore, when a Protection Register is locked, it cannot be
unlocked
April 2005
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Intel StrataFlash® Wireless Memory (L18)
Order Number: 251902, Revision: 009
Datasheet
INTEL [ INTEL ]
