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28F320B3 参数 Datasheet PDF下载

28F320B3图片预览
型号: 28F320B3
PDF下载: 下载PDF文件 查看货源
内容描述: 智能3高级启动块4-, 8-,16- , 32兆位闪存系列 [SMART 3 ADVANCED BOOT BLOCK 4-, 8-, 16-, 32-MBIT FLASH MEMORY FAMILY]
分类和应用: 闪存
文件页数/大小: 48 页 / 296 K
品牌: INTEL [ INTEL ]
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SMART 3 ADVANCED BOOT BLOCK  
1.2 Product Overview  
E
The Command User Interface (CUI) serves as the  
interface  
between  
the  
microprocessor  
or  
microcontroller and the internal operation of the  
flash memory. The internal Write State Machine  
(WSM) automatically executes the algorithms and  
timings necessary for program and erase  
operations, including verification, thereby un-  
burdening the microprocessor or microcontroller.  
The status register indicates the status of the WSM  
by signifying block erase or word program  
completion and status.  
Intel provides the most flexible voltage solution in  
the flash industry, providing three discrete voltage  
supply pins: VCC for read operation, VCCQ for output  
swing, and VPP for program and erase operation. All  
Smart  
3 Advanced Boot Block flash memory  
products provide program/erase capability at 2.7 V  
or 12 V [for fast production programming] and read  
with VCC at 2.7 V. Since many designs read from  
the flash memory a large percentage of the time,  
2.7 V VCC operation can provide substantial power  
savings.  
The Smart 3 Advanced Boot Block flash memory is  
also designed with an Automatic Power Savings  
(APS) feature which minimizes system current  
drain, allowing for very low power designs. This  
mode is entered following the completion of a read  
cycle (approximately 300 ns later).  
The Smart 3 Advanced Boot Block flash memory  
products are available in either x8 or x16 packages  
in the following densities: (see Ordering Information  
for availability.)  
The RP# pin provides additional protection against  
unwanted command writes that may occur during  
system reset and power-up/down sequences due to  
invalid system bus conditions (see Section 3.6).  
4-Mbit (4,194,304-bit) flash memory organized  
as 256 Kwords of 16 bits each or 512 Kbytes of  
8-bits each  
8-Mbit (8,388,608-bit) flash memory organized  
as 512 Kwords of 16 bits each or 1024 Kbytes  
of 8-bits each  
Section 3.0 gives detailed explanation of the  
different modes of operation. Complete current and  
voltage specifications can be found in the DC  
Characteristics section. Refer to AC Characteristics  
for read, program and erase performance  
specifications.  
16-Mbit  
(16,777,216-bit)  
flash  
memory  
organized as 1024 Kwords of 16 bits each or  
2048 Kbytes of 8-bits each  
32-Mbit  
(33,554,432-bit)  
flash  
memory  
organized as 2048 Kwords of 16 bits each or  
4096 Kbytes of 8-bits each  
2.0 PRODUCT DESCRIPTION  
This section explains device pin description and  
package pinouts.  
The parameter blocks are located at either the top  
(denoted by -T suffix) or the bottom (-B suffix) of the  
address map in order to accommodate different  
microprocessor protocols for kernel code location.  
The upper two (or lower two) parameter blocks can  
be locked to provide complete code security for  
system initialization code. Locking and unlocking is  
controlled by WP# (see Section 3.3 for details).  
2.1  
Package Pinouts  
The Smart 3 Advanced Boot Block flash memory is  
available in 40-lead TSOP (x8, Figure 1), 48-lead  
TSOP (x16, Figure 2) and 48-ball µBGA packages  
(x8 and x16, Figure 3 and Figure 4 respectively). In  
all figures, pin changes necessary for density  
upgrades have been circled.  
6
PRELIMINARY