E
1.0
INTRODUCTION
The documentation of the Intel 28F016XS Flash
memory device includes this datasheet, a detailed
user’s manual, a number of application notes and
design tools, all of which are referenced in
Appendix B.
The datasheet is intended to give an overview of
the chip feature-set and of the operating AC/DC
specifications. The
16-Mbit Flash Product Family
User’s Manual
provides complete descriptions of
the user modes, system interface examples and
detailed descriptions of all principles of operation. It
also contains the full list of software algorithm
flowcharts, and a brief section on compatibility with
the Intel 28F008SA.
Significant 28F016XS feature revisions occurred
between datasheet revisions 290532-001 and
290532-002. These revisions center around
removal of the following features:
•
•
•
•
•
All page buffer operations (read, write,
programming, Upload Device Information)
Command queuing
Software Sleep and Abort
Erase all Unlocked Blocks and Two-Byte Write
RY/BY# Configuration options
•
•
•
•
28F016XS FLASH MEMORY
The implementation of a new architecture, with
many enhanced features, will improve the device
operating characteristics and result in greater
product reliability and ease-of-use as compared to
other flash memories. Significant features of the
28F016XS as compared to previous asynchronous
flash memories include:
Synchronous Pipelined Read Interface
Significantly Improved Read and Program
Performance
SmartVoltage Technology
Selectable 3.3V or 5.0 V
CC
Selectable 5.0V or 12.0 V
PP
Block Program/Erase Protection
In addition, a significant 28F016XS change
occurred between datasheet revisions 290532-002
and 290532-003. This change centers around the
addition of a 3/5# pin to the device’s pinout
configuration. Figures 2 and 3 show the 3/5# pin
assignment for the TSOP and SSOP Type I
packages.
Intel recommends that all customers obtain the
latest revisions of 28F016XS documentation.
The 28F016XS’s synchronous pipelined interface
dramatically raises read performance far beyond
previously attainable levels. Addresses are
synchronously latched and data is read from a
28F016XS bank every 30 ns (5V V
CC
, SFI
Configuration = 2). This capability translates to zero
wait-state reads at clock rates up to 33 MHz at 5V
V
CC
, after an initial address pipeline fill delay and
assuming even and odd banks within the flash
memory are alternately accessed. Data is latched
and driven valid 20 ns (t
CHQV
) after a rising CLK
edge. The 28F016XS is capable of operating up to
50 MHz (5V V
CC
); its programmable SFI
Configuration enables system design flexibility,
optimizing the 28F016XS to a specific system clock
frequency. See Section 4.9, SFI Configuration
Table, for specific SFI Configurations for given
operating frequencies.
The SFI Configuration optimizes the 28F016XS for
a wide range of system operating frequencies. The
default SFI Configuration is 4, which allows system
boot from the 28F016XS at any frequency up to
50 MHz at 5V V
CC
. After initiating an access, data
is latched and begins driving on the data outputs
after a CLK count corresponding to the SFI
Configuration has elapsed. The 28F016XS will hold
data valid until CE# or OE# is deactivated or a CLK
count corresponding to the SFI Configuration for a
subsequent access has elapsed.
The CLK and ADV# inputs, new to the 28F016XS in
comparison to previous flash memories, control
address latching and device synchronization during
read operations. The CLK input controls the device
latencies, times out the SFI Configuration counter
and synchronizes data outputs. ADV# indicates the
presence of a valid address on the 28F016XS
7
1.1
Product Overview
The 28F016XS is a high-performance, 16-Mbit
(16,777,216-bit) block erasable nonvolatile random
access memory organized as either 1 Mword x 16
or 2 Mbyte x 8, subdivided into even and odd
banks. Address A
1
makes the bank selection. The
28F016XS includes sixteen 128-Kbyte (131,072
byte) blocks or sixteen 64-Kword (65,536 word)
blocks. Chip memory maps for x8 and x16 modes
are shown in Figures 4 and 5.
INTEL [ INTEL CORPORATION ]
