28F016XS FLASH MEMORY
E
REVISION HISTORY
Description
Number
-001
-002
Original Version
Removed support of the following features:
•
All page buffer operations (read, write, programming, Upload Device Information)
•
Command queuing
•
Software Sleep and Abort
•
Erase all Unlocked Blocks and Two-Byte Write
•
RY/BY# Configuration as part of the Device Configuration command
Changed definition of “NC.” Removed “No internal connection to die” from description.
Added “xx” to Upper Byte of Command (Data) Definition in Sections 4.3 and 4.4.
Modified parameters “V” and “I” of Section 5.1 to apply to “NC” pins.
Increased I
PPR
(V
PP
Read Current) for V
PP
> V
CC
to 200 µA at V
CC
= 3.3V/5.0V.
Changed V
CC
= 5.0V DC Characteristics (Section 5.5) marked with Note 1 to indicate
that these currents are specified for a CMOS rise/fall time (10% to 90%) of <5 ns
and a TTL rise/fall time of <10 ns.
Corrected t
PHCH
(RP# High to CLK) to be a “Min” specification at V
CC
= 3.3V/5.0V.
Corrected the graphical representation of t
WHCH
and t
EHCH
in Figures 15 and 16.
Increased Typical “Byte/Word Program Times” (t
WHRH1A
/t
WHRH1B
) for V
PP
= 5.0V (Sec.
5.13): t
WHRH1A
from 16.5 µs to 29.0 µs and t
WHRH1B
from 24.0 µs to 35.0 µs at V
CC
=
3.3V
t
WHRH1A
from 11.0 µs to 20.0 µs and t
WHRH1B
from 16.0 µs to 25.0 µs at V
CC
= 5.0V.
Increased Typical “Block Program Times” (t
WHRH2
/ t
WHRH3
) for V
PP
= 5.0V (Section 5.13):
t
WHRH2
from 2.2 sec to 3.8 sec and t
WHRH3
from 1.6 sec to 2.4 sec at V
CC
= 3.3V
t
WHRH2
from 1.6 sec to 2.8 sec and t
WHRH3
from 1.2 sec to 1.7 sec at V
CC
= 5.0V.
Changed “Time from Erase Suspend Command to WSM Ready” spec name to “Erase
Suspend Latency Time to Read;” Modified typical values and Added Min/Max values
at V
CC
=3.3/5.0V and V
PP
=5.0/12.0V (Section 5.13).
Minor cosmetic changes throughout document.
-003
Added 3/5# pin to Pinout Configuration (Figure 2), Product Overview (Section 1.1) and
Lead Descriptions (Section 2.1)
Modified Block Diagram (Figure 1): Removed Address Counter; Added 3/5# pin
Added 3/5# pin to Test Conditions of I
CCS
Specifications
Added 3/5# pin (Y) to Timing Nomenclature (Section 5.6)
Removed Note 7 of Section 5.7
Modified Device Configuration Code: Incorporated RY/BY# Configuration (Level Mode
support ONLY)
Modified Power-Up and Reset Timings (Section 5.10) to include 3/5# pin: Removed t
5VPH
and t
3VPH
specifications; Added t
PLYL
, t
PLYH
, t
YLPH
, and t
YHPH
specifications
Added SSOP pinout (Figure 2) and Mechanical Specifications
Corrected TSOP Mechanical Specification A1 from 0.50 mm to 0.050 mm (Section 6.0)
Minor cosmetic changes throughout document.
4
INTEL [ INTEL CORPORATION ]
