E
DQ
8-15
DQ
0-7
Output
Buffer
Output
Buffer
Input
Buffer
Data
Register
ID
Register
CLK
ADV#
28F016XS FLASH MEMORY
Input
Buffer
3/5#
I/O Logic
BYTE#
Output Multiplexer
CSR
CE0#
ESRs
OE#
CE
1
#
0-20
CUI
A
Data
Comparator
Input
Buffer
WE#
WP#
RP#
Even Address Latch
Y
Decoder
Y Gating/Sensing
128-Kbyte
128-Kbyte
WSM
Address
Register
128-Kbyte
128-Kbyte
X
Decoder
Even Bank
RY/BY#
VPP
3/5#
VCC
GND
Block 14
Odd Address Latch
X
Decoder
Odd Bank
Y
Decoder
Y Gating/Sensing
Block 15
Program/Erase
Voltage Switch
Block 0
Block 1
0532_01
Figure 1. 28F016XS Block Diagram
Architectural Evolution Includes Synchronous Pipelined Read Interface,
SmartVoltage Technology, and Extended Status Registers
9
4/15/97 9:41 AM
9053204.DOC
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