Ultra-Low Voltage Intel® Celeron® Processor — 650 MHz and 400 MHz
8.1.6
BCLK, BCLK# (I)
The BCLK and BCLK# signals determines the system bus frequency.
On systems with Differential Clocking, both system bus agents must receive these signals to drive
their outputs and latch their inputs on the BCLK rising edge and BCLK# falling edge. All external
timing parameters are specified with respect to the crossing point of the BCLK rising edge and
BCLK# falling edge.
On systems with Single Ended Clocking, both system bus agents must receive the BCLK signal to
drive their outputs and latch their inputs on the BCLK rising edge. All external timing parameters
are specified with respect to the BCLK signal. The BCLK# signal functions as the CLKREF input.
8.1.7
BERR# (I/O - AGTL)
The BERR# (Bus Error) signal is asserted to indicate an unrecoverable error without a bus protocol
violation. It may be driven by either system bus agent and must be connected to the appropriate
pins/balls of both agents, if used. However, the ULV Intel® Celeron® processors do not observe
assertions of the BERR# signal.
BERR# assertion conditions are defined by the system configuration. Configuration options enable
the BERR# driver as follows:
• Enabled or disabled
• Asserted optionally for internal errors along with IERR#
• Asserted optionally by the request initiator of a bus transaction after it observes an error
• Asserted by any bus agent when it observes an error in a bus transaction
8.1.8
BINIT# (I/O - AGTL)
The BINIT# (Bus Initialization) signal may be observed and driven by both system bus agents and
must be connected to the appropriate pins/balls of both agents, if used. If the BINIT# driver is
enabled during the power-on configuration, BINIT# is asserted to signal any bus condition that
prevents reliable future information.
If BINIT# is enabled during power-on configuration, and BINIT# is sampled asserted, all bus state
machines are reset and any data which was in transit is lost. All agents reset their rotating ID for
bus arbitration to the state after reset, and internal count information is lost. The L1 and L2 caches
are not affected.
If BINIT# is disabled during power-on configuration, a central agent may handle an assertion of
BINIT# as appropriate to the Machine Check Architecture (MCA) of the system.
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Datasheet
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