Ultra-Low Voltage Intel® Celeron® Processor — 650 MHz and 400 MHz
7.0
Processor Initialization and Configuration
7.1
Description
The ULV Intel® Celeron® processor has some configuration options that are determined by
hardware and some that are determined by software. The processor samples its hardware
configuration at reset on the active-to-inactive transition of RESET#. The P6 Family of Processors
Developer’s Manual describes these configuration options. Some of the configuration options for
the ULV Intel Celeron processor are described in the remainder of this section.
7.1.1
Quick Start Enable
Quick Start enabling is mandatory on the ULV Intel Celeron processor by strapping A15# low.
When the STPCLK# signal is asserted it will enter the Quick Start state when A15# is sampled
active on the RESET# signal’s active-to-inactive transition. The Quick Start state supports snoops
from the bus priority device but it does not support symmetric master snoops nor is the latching of
interrupts supported. A “1” in bit position 5 of the Power-on Configuration register indicates that
the Quick Start state has been enabled.
7.1.2
7.1.3
System Bus Frequency
The current generation ULV Intel Celeron processor will only function with a system bus
frequency of 100 MHz.
APIC Enable
The processor APIC must be hardware enabled by pulling the PICD[1:0] signals separately up to
1.5 V and supplying an active PICCLK to the processor. Software may be used to disable the APIC
if it is not being used, after PICD[1:0] are sampled high when RESET# is deasserted and the
processor has started executing instructions.
7.2
Clock Frequencies and Ratios
The ULV Intel Celeron processor uses a clock design in which the bus clock is multiplied by a ratio
to produce the processor’s internal (or core) clock. The ratio used is programmed into the processor
during manufacturing. The bus ratio programmed into the processor is visible in bit positions 22 to
25 and 27 of the Power-on Configuration register. Table 23 shows the 5-bit codes in the Power-on
Configuration register and their corresponding bus ratios.
Datasheet
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INTEL [ INTEL ]
