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250686-007 参数 Datasheet PDF下载

250686-007图片预览
型号: 250686-007
PDF下载: 下载PDF文件 查看货源
内容描述: 移动式英特尔奔腾4处理器-M [Mobile Intel Pentium4 Processor-M]
分类和应用:
文件页数/大小: 97 页 / 4754 K
品牌: INTEL [ INTEL ]
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Electrical Specifications  
Table 4. System Bus Pin Groups  
Signal Group  
Type  
Signals1  
Common  
clock  
AGTL+ Common Clock Input  
AGTL+ Common Clock I/O  
BPRI#, DEFER#, RESET#2, RS[2:0]#, RSP#, TRDY#  
AP[1:0]#, ADS#, BINIT#, BNR#, BPM[5:0]#2, BR0#2,  
DBSY#, DP[3:0]#, DRDY#, HIT#, HITM#, LOCK#,  
MCERR#  
Synchronous  
Signals  
Associated Strobe  
REQ[4:0]#, A[16:3]#5 ADSTB0#  
A[35:17]#5  
ADSTB1#  
AGTL+ Source Synchronous  
I/O  
Source  
Synchronous  
D[15:0]#, DBI0#  
D[31:16]#, DBI1#  
D[47:32]#, DBI2#  
D[63:48]#, DBI3#  
DSTBP0#, DSTBN0#  
DSTBP1#, DSTBN1#  
DSTBP2#, DSTBN2#  
DSTBP3#, DSTBN3#  
Common  
Clock  
AGTL+ Strobes  
ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]#  
A20M#, DPSLP#, GHI#, IGNNE#, INIT#5, LINT0/INTR,  
LINT1/NMI, SMI#5, SLP#, STPCLK#  
Asynchronous GTL+ Input4,5  
Asynchronous GTL+ Output4  
TAP Input4  
Asynchronous  
Asynchronous FERR#/PBE#, IERR#2, THERMTRIP#, PROCHOT#  
Synchronous  
TCK, TDI, TMS, TRST#  
to TCK  
Synchronous  
TDO  
TAP Output4  
to TCK  
System Bus Clock  
N/A  
BCLK[1:0], ITP_CLK[1:0]3  
VCC, VCCA, VCCIOPLL, VCCVID, VID[4:0], VSS, VSSA  
GTLREF[3:0], COMP[1:0], NC, TESTHI[5:0],  
TESTHI[10:8], ITPCLKOUT[1:0], PWRGOOD,  
,
Power/Other  
N/A  
THERMDA, THERMDC, SKTOCC#, VCC_SENSE  
V
,
SS_SENSE, BSEL[1:0], DBR#3  
NOTES:  
1. Refer to Section 5.2 for signal descriptions.  
2. These AGTL+ signals do not have on-die termination. Refer to Section 2.5 for termination requirements.  
3. In processor systems where there is no debug port implemented on the system board, these signals are used  
to support a debug port interposer. In systems with the debug port implemented on the system board, these  
signals are no connects.  
4. These signal groups are not terminated by the processor. Signals not driven by the ICH3-M component must  
be terminated on the system board. Refer to Section 2.5 and the Mobile Intel Pentium 4 Processor-M and  
Intel 845MP/845MZ Chipset Platform Design Guide for termination requirements and further details.  
5. The value of these pins during the active-to-inactive edge of RESET# defines the processor configuration  
options. See Section 7.1 for details.  
Mobile Intel Pentium 4 Processor-M Datasheet  
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