Intel
®
Cyclone
®
10 LP Device Overview
C10LP51001 | 2020.05.21
Embedded Multipliers
Each embedded multiplier block in Intel Cyclone 10 LP devices supports one individual
18 × 18-bit multiplier or two individual 9 × 9-bit multipliers. You can cascade the
multiplier blocks to form wider or deeper logic structures.
You can control the operation of the embedded multiplier blocks using the following
options:
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Parameterize the relevant IP cores with the Intel Quartus Prime parameter editor
Infer the multipliers directly with VHDL or Verilog HDL
Intel and partners offer popular DSP IPs for Intel Cyclone 10 LP devices, including:
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Finite impulse response (FIR)
Fast Fourier transform (FFT)
Numerically controlled oscillator (NCO) functions
For a streamlined DSP design flow, the DSP Builder tool integrates the Intel Quartus
Prime software with MathWorks Simulink and MATLAB design environments.
Embedded Memory Blocks
The embedded memory structure consists of M9K memory blocks columns. Each M9K
memory block of a Intel Cyclone 10 LP device provides 9 Kb of on-chip memory. You
can cascade the memory blocks to form wider or deeper logic structures.
You can configure the M9K memory blocks as RAM, FIFO buffers, or ROM.
Table 4.
M9K Operation Modes and Port Widths
Operation Modes
Single port
Simple dual port
True dual port
Port Widths
×1, ×2, ×4, ×8, ×9, ×16, ×18, ×32, and ×36
×1, ×2, ×4, ×8, ×9, ×16, ×18, ×32, and ×36
×1, ×2, ×4, ×8, ×9, ×16, and ×18
Clocking and PLL
Intel Cyclone 10 LP devices feature global clock (GCLK) networks, dedicated clock
pins, and general purpose PLLs.
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Up to 20 GCLK networks that drive throughout the device
Up to 15 dedicated clock pins
Up to four general purpose PLLs with five outputs per PLL
The PLLs provide robust clock management and synthesis for the Intel Cyclone 10 LP
device. You can dynamically reconfigure the PLLs in user mode to change the clock
phase or frequency.
Intel
®
Cyclone
®
10 LP Device Overview
8
INTEL [ INTEL CORPORATION ]
