Intel
®
Cyclone
®
10 LP Device Overview
C10LP51001 | 2020.05.21
Summary of Intel Cyclone 10 LP Features
Table 1.
Summary of Features for Intel Cyclone 10 LP Devices
Feature
Technology
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Description
Low-cost, low-power FPGA fabric
1.0 V and 1.2 V core voltage options
Available in commercial, industrial, and automotive temperature grades
Several package types and footprints:
— FineLine BGA (FBGA)
— Enhanced Thin Quad Flat Pack (EQFP)
— Ultra FineLine BGA (UBGA)
— Micro FineLine BGA (MBGA)
Multiple device densities with pin migration capability
RoHS6 compliance
Logic elements (LEs)—four-input look-up table (LUT) and register
Abundant routing/metal interconnect between all LEs
M9K—9-kilobits (Kb) of embedded SRAM memory blocks, cascadable
Configurable as RAM (single-port, simple dual port, or true dual port), FIFO buffers, or ROM
One 18 × 18 or two 9 × 9 multiplier modes, cascadable
Complete suite of DSP IPs for algorithmic acceleration
Global clocks that drive throughout entire device, feeding all device quadrants
Up to 15 dedicated clock pins that can drive up to 20 global clocks
Up to four general purpose PLLs
Provides robust clock management and synthesis
Multiple I/O standards support
Programmable I/O features
True LVDS and emulated LVDS transmitters and receivers
On-chip termination (OCT)
Packaging
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Core architecture
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Internal memory
blocks
Embedded multiplier
blocks
Clock networks
Phase-locked loops
(PLLs)
General-purpose I/Os
(GPIOs)
SEU mitigation
Configuration
SEU detection during configuration and operation
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Active serial (AS), passive serial (PS), fast passive parallel (FPP)
JTAG configuration scheme
Configuration data decompression
Remote system upgrade
Intel
®
Cyclone
®
10 LP Device Overview
4
INTEL [ INTEL CORPORATION ]
