A10-DATASHEET
2015.12.31
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FPP Configuration Timing when DCLK-to-DATA[] >1
FPP Configuration Timing when DCLK-to-DATA[] >1
Table 77: FPP Timing Parameters When the DCLK-to-DATA[] Ratio is >1 for Arria 10 Devices—Preliminary
Use these timing parameters when you use the decompression and design security features.
Symbol
Parameter
nCONFIGlow to CONF_DONElow
nCONFIGlow to nSTATUSlow
nCONFIGlow pulse width
Minimum
Maximum
Unit
ns
ns
μs
μs
μs
μs
μs
ns
s
tCF2CD
tCF2ST0
tCFG
tSTATUS
tCF2ST1
—
—
600
600
—
2
nSTATUSlow pulse width
268
—
3,000 (98)
3,000 (98)
—
nCONFIGhigh to nSTATUShigh
nCONFIGhigh to first rising edge on DCLK
nSTATUShigh to first rising edge of DCLK
DATA[]setup time before rising edge on DCLK
DATA[]hold time after rising edge on DCLK
DCLKhigh time
(99)
tCF2CK
tST2CK
tDSU
tDH
3,010
10
(99)
—
5.5
—
(100)
N–1/fDCLK
—
tCH
0.45 × 1/fMAX
—
s
tCL
DCLKlow time
0.45 × 1/fMAX
—
s
tCLK
fMAX
tR
DCLKperiod
1/fMAX
—
—
s
DCLKfrequency (FPP ×8/×16/×32)
Input rise time
100
40
MHz
ns
ns
μs
—
tF
Input fall time
CONF_DONEhigh to user mode (101)
—
40
tCD2UM
175
830
(98)
(99)
You can obtain this value if you do not delay configuration by extending the nCONFIGor nSTATUSlow pulse width.
If nSTATUSis monitored, follow the tST2CK specification. If nSTATUSis not monitored, follow the tCF2CK specification.
N is the DCLK-to-DATAratio and fDCLK is the DCLKfrequency the system is operating.
(100)
(101)
The minimum and maximum numbers apply only if you use the internal oscillator as the clock source for initializing the device.
Arria 10 Device Datasheet
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